From 03e971cd23e96b9293fc3ecc420f56ad91326cd9 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 7 Mar 2017 14:02:23 +0530 Subject: soc/intel/common/block: Add cache as ram init and teardown code Create sample model for common car init and teardown programming. TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED and CAR_NEM configs till post code 0x2a. Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/18381 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/skylake/romstage/car_stage_fsp20.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/skylake/romstage') diff --git a/src/soc/intel/skylake/romstage/car_stage_fsp20.S b/src/soc/intel/skylake/romstage/car_stage_fsp20.S index c6401fa597..5ef8bd61bf 100644 --- a/src/soc/intel/skylake/romstage/car_stage_fsp20.S +++ b/src/soc/intel/skylake/romstage/car_stage_fsp20.S @@ -37,7 +37,8 @@ car_stage_entry: /* Switch to the stack in RAM */ movl %eax, %esp - #include + /* chipset_teardown_car() is expected to disable cache-as-ram. */ + call chipset_teardown_car /* Display the MTRRs */ call soc_display_mtrrs -- cgit v1.2.3