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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-12-19 16:19:44 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-18 18:02:27 +0000
commit66c6413c69abb7335efc4ea07f4c811c042704b6 (patch)
tree06d58b85da4c779cca7b78e33a069ea03a4e69e4 /src/soc/intel/skylake/pmc.c
parentc4a6628a6fe4f5400b7abe1478d0b0b21cb8200f (diff)
ACPI: Refactor ChromeOS specific ACPI GNVS
The layout of GNVS has expectation for a fixed size array for chromeos_acpi_t. This allows us to reduce the exposure of <chromeos/gnvs.h>. If chromeos_acpi_t was the last entry in struct global_nvs padding at the end is also removed. If device_nvs_t exists, place a properly sized reserve for chromeos_acpi_t in the middle. Allocation from cbmem is adjusted such that it matches exactly the OperationRegion size defined inside the ASL. Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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