diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-03-21 15:38:06 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-04-26 16:49:13 +0000 |
| commit | c3385070d6e86dbde71dddbdef94ffa5579f9d11 (patch) | |
| tree | e2d65c2c0550b67092d008ca31c3c22e11b932f0 /src/soc/intel/skylake/include | |
| parent | 9df72e0471296d9bc2981646490c1f8b5b1e54e0 (diff) | |
soc/{amd,intel}/chip: Use local include for chip.h
Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/fsp11/soc/ramstage.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/fsp20/soc/ramstage.h | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h index 3ab0efa7e5..2071d58b49 100644 --- a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h @@ -17,11 +17,12 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include <chip.h> #include <device/device.h> #include <fsp/ramstage.h> #include <fsp/soc_binding.h> +#include "../../../chip.h" + #define FSP_SIL_UPD SILICON_INIT_UPD #define FSP_MEM_UPD MEMORY_INIT_UPD diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h index e75b350049..e5660a6f66 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h @@ -17,11 +17,12 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include <chip.h> #include <device/device.h> #include <fsp/api.h> #include <fsp/util.h> +#include "../../../chip.h" + #define FSP_SIL_UPD FSP_S_CONFIG #define FSP_MEM_UPD FSP_M_CONFIG |