diff options
| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2016-08-24 20:48:46 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-15 00:46:11 +0200 |
| commit | 5bf42c6c23b462d9292e6854d3f334cf17e42825 (patch) | |
| tree | 2a95d06c128f2fe97027e7fc46e9368399ab8504 /src/soc/intel/skylake/include | |
| parent | 69966ccb5de0addda131f313b20515bfa0cb00c8 (diff) | |
soc/intel/skylake: Add FSP 2.0 support in romstage
Populate SoC related Memory initialization params.
Post memory init, set DISB, setup stack and MTRRs using the postcar
funtions provided in postcar_loader.c.
TEST=Build and boot kunimitsu, dram initialization done.
ramstage is loaded.
Change-Id: I8d943e29b6e118986189166d92c7891ab6642193
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16315
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/fsp20/soc/romstage.h | 10 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pm.h | 3 |
2 files changed, 11 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h index d48ac67ab3..08753f1ee9 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h @@ -21,10 +21,16 @@ #include <fsp/api.h> asmlinkage void *car_stage_c_entry(void); -void mainboard_memory_init_params(struct FSPM_UPD *mupd); - +void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read_wpsr(u8 *sr); +/* Board type */ +enum board_type { + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 +}; #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index e0bf8b0c3a..235ad898e0 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -183,6 +183,9 @@ uint8_t *pmc_mmio_regs(void); /* Get base address of TCO I/O registers. */ uint16_t smbus_tco_regs(void); +/* Set the DISB after DRAM init */ +void pmc_set_disb(void); + static inline int deep_s3_enabled(void) { uint32_t deep_s3_pol; |