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authorrsatapat <rishavnath.satapathy@intel.com>2015-06-24 20:49:16 +0530
committerPatrick Georgi <pgeorgi@google.com>2015-07-21 20:12:11 +0200
commit1b9635de6613548449cd2689d212cd6f01dbfd54 (patch)
tree03125c22c37c3dac80bfe8f9b646feff2c1305b4 /src/soc/intel/skylake/include
parent5c56ce13f4a81970ed8c9a2987c2ea55376da52d (diff)
Skylake: Initialize GPIOs for UART2
FSP will initialize GPIOs during TempRamInit. So configure LPSS UART2 GPIOs in native mode after TempRamInit. BRANCH=none BUG=chrome-os-partner:41374 EST=Build and boot on RVP3. Check LPSS logs on UART2 Change-Id: I8016dd76a5bc06e90f9460273be7e83c5e8f8bb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eb72e715ef3f566e900727ac8b9494bca1d5971c Original-Change-Id: If1b1a1047ebd5e5f170d91972d11c51aa6fd84a9 Original-Signed-off-by: rsatapat <rishavnath.satapathy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281604 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10995 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r--src/soc/intel/skylake/include/soc/gpio.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index efc666f4cd..03ed11988d 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -257,6 +257,18 @@ typedef struct {
.owner = GPIO_OWNER_GPIO, \
.conf1 = GPIO_SENSE_DISABLE }
+/* Number of pins used by SerialIo controllers */
+#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4
+#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2
+
+/* Below defines are based on GPIO_CONFIG structure fields */
+#define GPIO_CONF_PAD_MODE_MASK 0xF
+#define GPIO_CONF_PAD_MODE_BIT_POS 0
+
+/* GPIO Pad Mode */
+#define B_PCH_GPIO_PAD_MODE (0x1000 | 0x800 | 0x400)
+#define N_PCH_GPIO_PAD_MODE 10
+
struct gpio_config {
u8 gpio;
u32 conf0;