From 1b9635de6613548449cd2689d212cd6f01dbfd54 Mon Sep 17 00:00:00 2001 From: rsatapat Date: Wed, 24 Jun 2015 20:49:16 +0530 Subject: Skylake: Initialize GPIOs for UART2 FSP will initialize GPIOs during TempRamInit. So configure LPSS UART2 GPIOs in native mode after TempRamInit. BRANCH=none BUG=chrome-os-partner:41374 EST=Build and boot on RVP3. Check LPSS logs on UART2 Change-Id: I8016dd76a5bc06e90f9460273be7e83c5e8f8bb1 Signed-off-by: Patrick Georgi Original-Commit-Id: eb72e715ef3f566e900727ac8b9494bca1d5971c Original-Change-Id: If1b1a1047ebd5e5f170d91972d11c51aa6fd84a9 Original-Signed-off-by: rsatapat Original-Reviewed-on: https://chromium-review.googlesource.com/281604 Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Wenkai Du Original-Tested-by: Wenkai Du Reviewed-on: http://review.coreboot.org/10995 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/skylake/include/soc/gpio.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/soc/intel/skylake/include') diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index efc666f4cd..03ed11988d 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -257,6 +257,18 @@ typedef struct { .owner = GPIO_OWNER_GPIO, \ .conf1 = GPIO_SENSE_DISABLE } +/* Number of pins used by SerialIo controllers */ +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4 +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2 + +/* Below defines are based on GPIO_CONFIG structure fields */ +#define GPIO_CONF_PAD_MODE_MASK 0xF +#define GPIO_CONF_PAD_MODE_BIT_POS 0 + +/* GPIO Pad Mode */ +#define B_PCH_GPIO_PAD_MODE (0x1000 | 0x800 | 0x400) +#define N_PCH_GPIO_PAD_MODE 10 + struct gpio_config { u8 gpio; u32 conf0; -- cgit v1.2.3