diff options
author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-25 07:41:54 -0700 |
---|---|---|
committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-08-05 01:50:45 +0200 |
commit | 102f6253600cfa3f741c0d1d126436d612daa203 (patch) | |
tree | dc3d0c6376b405dc053e4f4c9c864d30cf4737eb /src/soc/intel/quark/romstage | |
parent | 6e05c33626e128c383470579f423b1ee569302ba (diff) |
soc/intel/quark: Add FSP 2.0 boot block support
Add the pieces necessary to successfully build and run bootblock using
the FSP 2.0 build.
TEST=Build and run bootblock on Galileo Gen2
Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/romstage')
-rw-r--r-- | src/soc/intel/quark/romstage/Makefile.inc | 3 | ||||
-rw-r--r-- | src/soc/intel/quark/romstage/car_stage_entry.S | 2 | ||||
-rw-r--r-- | src/soc/intel/quark/romstage/fsp1_1.c | 8 | ||||
-rw-r--r-- | src/soc/intel/quark/romstage/fsp2_0.c | 25 |
4 files changed, 38 insertions, 0 deletions
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 635da83c64..329138b3be 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -16,7 +16,10 @@ romstage-y += car.c romstage-y += car_stage_entry.S romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c romstage-y += romstage.c + +postcar-y += mtrr.c diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S index d0a0db0f5d..b8207117fa 100644 --- a/src/soc/intel/quark/romstage/car_stage_entry.S +++ b/src/soc/intel/quark/romstage/car_stage_entry.S @@ -29,9 +29,11 @@ car_stage_entry: /* Enter the C code */ call car_stage_c_entry +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #if !ENV_VERSTAGE #include "src/drivers/intel/fsp1_1/after_raminit.S" #endif +#endif /* The code should never reach this point */ movb $0x69, %ah diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c index 73910a0775..16d1d063c3 100644 --- a/src/soc/intel/quark/romstage/fsp1_1.c +++ b/src/soc/intel/quark/romstage/fsp1_1.c @@ -19,9 +19,11 @@ #include <console/console.h> #include <cbfs.h> #include "../chip.h" +#include <fsp/memmap.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/pci_devs.h> +#include <soc/QuarkNcSocId.h> #include <soc/romstage.h> #include <string.h> @@ -65,6 +67,12 @@ struct chipset_power_state *fill_power_state(void) return ps; } +size_t mmap_region_granularity(void) +{ + /* Align to 8 MiB by default */ + return 8 << 20; +} + /* Initialize the UPD parameters for MemoryInit */ void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd) diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c new file mode 100644 index 0000000000..a77349897d --- /dev/null +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> +#include <soc/romstage.h> + +asmlinkage void *car_stage_c_entry(void) +{ + post_code(0x20); + console_init(); + return NULL; +} |