From 102f6253600cfa3f741c0d1d126436d612daa203 Mon Sep 17 00:00:00 2001
From: Lee Leahy <leroy.p.leahy@intel.com>
Date: Mon, 25 Jul 2016 07:41:54 -0700
Subject: soc/intel/quark: Add FSP 2.0 boot block support

Add the pieces necessary to successfully build and run bootblock using
the FSP 2.0 build.

TEST=Build and run bootblock on Galileo Gen2

Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
---
 src/soc/intel/quark/romstage/Makefile.inc      |  3 +++
 src/soc/intel/quark/romstage/car_stage_entry.S |  2 ++
 src/soc/intel/quark/romstage/fsp1_1.c          |  8 ++++++++
 src/soc/intel/quark/romstage/fsp2_0.c          | 25 +++++++++++++++++++++++++
 4 files changed, 38 insertions(+)
 create mode 100644 src/soc/intel/quark/romstage/fsp2_0.c

(limited to 'src/soc/intel/quark/romstage')

diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index 635da83c64..329138b3be 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -16,7 +16,10 @@
 romstage-y += car.c
 romstage-y += car_stage_entry.S
 romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c
 romstage-y += mtrr.c
 romstage-y += pcie.c
 romstage-y += report_platform.c
 romstage-y += romstage.c
+
+postcar-y += mtrr.c
diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S
index d0a0db0f5d..b8207117fa 100644
--- a/src/soc/intel/quark/romstage/car_stage_entry.S
+++ b/src/soc/intel/quark/romstage/car_stage_entry.S
@@ -29,8 +29,10 @@ car_stage_entry:
 	/* Enter the C code */
 	call	car_stage_c_entry
 
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
 #if !ENV_VERSTAGE
 #include "src/drivers/intel/fsp1_1/after_raminit.S"
+#endif
 #endif
 
 	/* The code should never reach this point */
diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c
index 73910a0775..16d1d063c3 100644
--- a/src/soc/intel/quark/romstage/fsp1_1.c
+++ b/src/soc/intel/quark/romstage/fsp1_1.c
@@ -19,9 +19,11 @@
 #include <console/console.h>
 #include <cbfs.h>
 #include "../chip.h"
+#include <fsp/memmap.h>
 #include <fsp/util.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
+#include <soc/QuarkNcSocId.h>
 #include <soc/romstage.h>
 #include <string.h>
 
@@ -65,6 +67,12 @@ struct chipset_power_state *fill_power_state(void)
 	return ps;
 }
 
+size_t mmap_region_granularity(void)
+{
+	/* Align to 8 MiB by default */
+	return 8 << 20;
+}
+
 /* Initialize the UPD parameters for MemoryInit */
 void soc_memory_init_params(struct romstage_params *params,
 			    MEMORY_INIT_UPD *upd)
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
new file mode 100644
index 0000000000..a77349897d
--- /dev/null
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/romstage.h>
+
+asmlinkage void *car_stage_c_entry(void)
+{
+	post_code(0x20);
+	console_init();
+	return NULL;
+}
-- 
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