soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage

List of changes:
1. Add required SoC programming till ramstage.
2. Include only required headers into include/soc.
3. Skeleton code used to call FSP-S API.

BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
     for PTL using google/fatcat mainboard.

Change-Id: I61930726ad0c765bfa1d72c5df893262be884834
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84332
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

1 files changed, 10 insertions, 0 deletions

diff --git a/src/soc/intel/pantherlake/tcss.c b/src/soc/intel/pantherlake/tcss.c
new file mode 100644
index 0000000000..99cbdd2d67
--- /dev/null
+++ b/src/soc/intel/pantherlake/tcss.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/tcss.h>
+#include <soc/soc_chip.h>
+
+const struct soc_tcss_ops tcss_ops = {
+/* TODO: Implement AUX BIAS PAD Programming if required */
+	.configure_aux_bias_pads = NULL,
+	.valid_tbt_auth = NULL,
+};