From 95cf9c0052234cf19599c03ea214eff4a6ed3b65 Mon Sep 17 00:00:00 2001 From: Saurabh Mishra Date: Thu, 12 Sep 2024 10:52:56 +0530 Subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I61930726ad0c765bfa1d72c5df893262be884834 Signed-off-by: Saurabh Mishra Reviewed-on: https://review.coreboot.org/c/coreboot/+/84332 Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/pantherlake/tcss.c | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 src/soc/intel/pantherlake/tcss.c (limited to 'src/soc/intel/pantherlake/tcss.c') diff --git a/src/soc/intel/pantherlake/tcss.c b/src/soc/intel/pantherlake/tcss.c new file mode 100644 index 0000000000..99cbdd2d67 --- /dev/null +++ b/src/soc/intel/pantherlake/tcss.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +const struct soc_tcss_ops tcss_ops = { +/* TODO: Implement AUX BIAS PAD Programming if required */ + .configure_aux_bias_pads = NULL, + .valid_tbt_auth = NULL, +}; -- cgit v1.2.3