soc/intel/meteorlake: Hook up common code for thermal configuration

Thermal configuration registers are now located behind PMC PWRMBASE
for MeteorLake as well (same as ADL). Hence, using thermal common code
to sets the thermal low threshold as per mainboard provided
`pch_thermal_trip`.

Note: These thermal configuration registers are RW/O hence, setting
those early prior to FSP-S helps coreboot to set the desired low
thermal threshold for the platform.

TEST=Dump thermal configuration registers PWRMBASE+0x150c etc on
Google/rex prior to FSP-S shows that registers are now programmed
based on 'pch_thermal_trip' and lock register BIT31 is set.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1d6b179a1ed43f00416d90490e0a91710648655e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67462
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

1 files changed, 9 insertions, 0 deletions

diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c
index 95a6e9cd6b..2ac5021b42 100644
--- a/src/soc/intel/meteorlake/romstage/romstage.c
+++ b/src/soc/intel/meteorlake/romstage/romstage.c
@@ -8,6 +8,7 @@
 #include <intelblocks/cse.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/smbus.h>
+#include <intelblocks/thermal.h>
 #include <memory_info.h>
 #include <soc/intel/common/smbios.h>
 #include <soc/iomap.h>
@@ -132,6 +133,14 @@ void mainboard_romstage_entry(void)
 			cse_fw_sync();
 	}
 
+	/*
+	 * Set low maximum temp threshold value used for dynamic thermal sensor
+	 * shutdown consideration.
+	 *
+	 * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
+	 * thermal sensor when CPU is in a C-state and LTT >= DTS Temp.
+	 */
+	pch_thermal_configuration();
 	fsp_memory_init(s3wake);
 	pmc_set_disb();
 	if (!s3wake)