From 2bce51ea2a105e3a78b321411c053760aa6b8de7 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 8 Sep 2022 13:29:22 -0700 Subject: soc/intel/meteorlake: Hook up common code for thermal configuration Thermal configuration registers are now located behind PMC PWRMBASE for MeteorLake as well (same as ADL). Hence, using thermal common code to sets the thermal low threshold as per mainboard provided `pch_thermal_trip`. Note: These thermal configuration registers are RW/O hence, setting those early prior to FSP-S helps coreboot to set the desired low thermal threshold for the platform. TEST=Dump thermal configuration registers PWRMBASE+0x150c etc on Google/rex prior to FSP-S shows that registers are now programmed based on 'pch_thermal_trip' and lock register BIT31 is set. Signed-off-by: Subrata Banik Change-Id: I1d6b179a1ed43f00416d90490e0a91710648655e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67462 Reviewed-by: Tarun Tuli Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Eric Lai --- src/soc/intel/meteorlake/romstage/romstage.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/soc/intel/meteorlake') diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index 95a6e9cd6b..2ac5021b42 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -132,6 +133,14 @@ void mainboard_romstage_entry(void) cse_fw_sync(); } + /* + * Set low maximum temp threshold value used for dynamic thermal sensor + * shutdown consideration. + * + * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the + * thermal sensor when CPU is in a C-state and LTT >= DTS Temp. + */ + pch_thermal_configuration(); fsp_memory_init(s3wake); pmc_set_disb(); if (!s3wake) -- cgit v1.2.3