diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2022-05-08 00:27:31 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-06-29 05:29:00 +0000 |
| commit | e02fd83eba7bb20956e0d1d1ef18f28f146b0340 (patch) | |
| tree | 87a53885dc721ce2c9a808202ee1598269f152a2 /src/soc/intel/meteorlake/include | |
| parent | 91ffac8c04776e1e663c5987ea718522f605a9b4 (diff) | |
soc/intel/mtl/acpi: Add SoC ACPI directory for Meteor Lake
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH,
LAN, HDA etc.
BUG=b:224325352
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Change-Id: Iebe3d38f50e202d75add88f336b5f3e9ba9f5a22
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64168
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/meteorlake/include')
| -rw-r--r-- | src/soc/intel/meteorlake/include/soc/tcss.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/include/soc/tcss.h b/src/soc/intel/meteorlake/include/soc/tcss.h index 014e3076e6..439606c6af 100644 --- a/src/soc/intel/meteorlake/include/soc/tcss.h +++ b/src/soc/intel/meteorlake/include/soc/tcss.h @@ -13,4 +13,24 @@ #define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 0x1088 #define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4) +/* + * The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency + * optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream + * port of the USB4/TBT topology. + */ +/* Number of microseconds to wait after a conventional reset */ +#define FW_RESET_TIME 50000 + +/* Number of microseconds to wait after data link layer active report */ +#define FW_DL_UP_TIME 1 + +/* Number of microseconds to wait after a function level reset */ +#define FW_FLR_RESET_TIME 1 + +/* Number of microseconds to wait from D3 hot to D0 transition */ +#define FW_D3HOT_TO_D0_TIME 50000 + +/* Number of microseconds to wait after setting the VF enable bit */ +#define FW_VF_ENABLE_TIME 1 + #endif /* _SOC_TCSS_H_ */ |