soc/intel/mtl: Do initial Meteor Lake SoC commit till ramstage

List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Fill required FSP-S UPD to call FSP-S API

BUG=b:224325352
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63364
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

14 files changed, 358 insertions, 1 deletions

diff --git a/src/soc/intel/meteorlake/include/soc/cpu.h b/src/soc/intel/meteorlake/include/soc/cpu.h
new file mode 100644
index 0000000000..1a6cd6a69e
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/cpu.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_METEORLAKE_CPU_H_
+#define _SOC_METEORLAKE_CPU_H_
+
+/* Latency times in us */
+#define C1_LATENCY	1
+#define C6_LATENCY	127
+#define C7_LATENCY	253
+#define C8_LATENCY	260
+#define C9_LATENCY	487
+#define C10_LATENCY	1048
+
+/* Power in units of mW */
+#define C1_POWER	0x3e8
+#define C6_POWER	0x15e
+#define C7_POWER	0xc8
+#define C8_POWER	0xc8
+#define C9_POWER	0xc8
+#define C10_POWER	0xc8
+
+/* Get a bitmask of supported LPM states */
+uint8_t get_supported_lpm_mask(void);
+
+#endif /* _SOC_METEORLAKE_CPU_H_ */
diff --git a/src/soc/intel/meteorlake/include/soc/iomap.h b/src/soc/intel/meteorlake/include/soc/iomap.h
index c50fdb26f3..a2df40ccb4 100644
--- a/src/soc/intel/meteorlake/include/soc/iomap.h
+++ b/src/soc/intel/meteorlake/include/soc/iomap.h
@@ -61,6 +61,14 @@
 #define P2SB_BAR		CONFIG_PCR_BASE_ADDRESS
 #define P2SB_SIZE		(16 * MiB)
 
+#define IOE_PCR_ABOVE_4G_BASE_ADDR	0x3fff0000000
+#define IOE_P2SB_BAR		IOE_PCR_ABOVE_4G_BASE_ADDR
+#define IOE_P2SB_SIZE		(256 * MiB)
+
+#define IOM_BASE_ADDR		0x3fff0aa0000
+#define IOM_BASE_SIZE		0x1600
+#define IOM_BASE_ADDR_MAX	0x3fff0aa15ff
+
 /*
  * I/O port address space
  */
diff --git a/src/soc/intel/meteorlake/include/soc/irq.h b/src/soc/intel/meteorlake/include/soc/irq.h
new file mode 100644
index 0000000000..edc09a1332
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/irq.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_IRQ_H_
+#define _SOC_IRQ_H_
+
+#define GPIO_IRQ14	14
+#define GPIO_IRQ15	15
+
+#define PCH_IRQ10	10
+#define PCH_IRQ11	11
+
+#define LPSS_UART0_IRQ	16
+#define LPSS_UART1_IRQ	17
+#define LPSS_UART2_IRQ	31
+
+#endif
diff --git a/src/soc/intel/meteorlake/include/soc/itss.h b/src/soc/intel/meteorlake/include/soc/itss.h
new file mode 100644
index 0000000000..74ee5ab8c8
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/itss.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_INTEL_MTL_ITSS_H
+#define SOC_INTEL_MTL_ITSS_H
+
+#define GPIO_IRQ_START	50
+#define GPIO_IRQ_END	ITSS_MAX_IRQ
+
+#define ITSS_MAX_IRQ	119
+#define IRQS_PER_IPC	32
+#define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
+
+#endif	/* SOC_INTEL_ADL_ITSS_H */
diff --git a/src/soc/intel/meteorlake/include/soc/me.h b/src/soc/intel/meteorlake/include/soc/me.h
new file mode 100644
index 0000000000..17cf5cd60b
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/me.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _METEORLAKE_ME_H_
+#define _METEORLAKE_ME_H_
+
+#include <stdint.h>
+
+/* ME Host Firmware Status register 1 */
+union me_hfsts1 {
+	u32 data;
+	struct {
+		u32 working_state: 4;
+		u32 mfg_mode: 1;
+		u32 fpt_bad: 1;
+		u32 operation_state: 3;
+		u32 fw_init_complete: 1;
+		u32 ft_bup_ld_flr: 1;
+		u32 update_in_progress: 1;
+		u32 error_code: 4;
+		u32 operation_mode: 4;
+		u32 reset_count: 4;
+		u32 boot_options_present: 1;
+		u32 invoke_enhance_dbg_mode: 1;
+		u32 bist_test_state: 1;
+		u32 bist_reset_request: 1;
+		u32 current_power_source: 2;
+		u32 reserved: 1;
+		u32 d0i3_support_valid: 1;
+	} __packed fields;
+};
+
+/* ME Host Firmware Status Register 3 */
+union me_hfsts3 {
+	u32 data;
+	struct {
+		u32 reserved_0: 4;
+		u32 fw_sku: 3;
+		u32 reserved_7: 2;
+		u32 reserved_9: 2;
+		u32 resered_11: 3;
+		u32 resered_14: 16;
+		u32 reserved_30: 2;
+	} __packed fields;
+};
+#endif
diff --git a/src/soc/intel/meteorlake/include/soc/nvs.h b/src/soc/intel/meteorlake/include/soc/nvs.h
new file mode 100644
index 0000000000..512945898e
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/nvs.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_NVS_H_
+#define _SOC_NVS_H_
+
+#include <intelblocks/nvs.h>
+
+#endif
diff --git a/src/soc/intel/meteorlake/include/soc/p2sb.h b/src/soc/intel/meteorlake/include/soc/p2sb.h
index c515475f1b..79ec2b1737 100644
--- a/src/soc/intel/meteorlake/include/soc/p2sb.h
+++ b/src/soc/intel/meteorlake/include/soc/p2sb.h
@@ -8,4 +8,6 @@
 
 #define PCH_P2SB_EPMASK0		0x220
 
+extern struct device_operations ioe_p2sb_ops;
+
 #endif
diff --git a/src/soc/intel/meteorlake/include/soc/pci_devs.h b/src/soc/intel/meteorlake/include/soc/pci_devs.h
index 4d0e3438b5..b139da4f4f 100644
--- a/src/soc/intel/meteorlake/include/soc/pci_devs.h
+++ b/src/soc/intel/meteorlake/include/soc/pci_devs.h
@@ -8,7 +8,7 @@
 #define _PCI_DEVFN(slot, func)	PCI_DEVFN(PCI_DEV_SLOT_ ## slot, func)
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#define _PCI_DEV(slot, func)	pcidev_path_on_root(_PCI_DEVFN(slot, func), __func__)
+#define _PCI_DEV(slot, func)	pcidev_path_on_root_debug(_PCI_DEVFN(slot, func), __func__)
 #else
 #define _PCI_DEV(slot, func)	PCI_DEV(0, PCI_DEV_SLOT_ ## slot, func)
 #endif
diff --git a/src/soc/intel/meteorlake/include/soc/pcie.h b/src/soc/intel/meteorlake/include/soc/pcie.h
new file mode 100644
index 0000000000..f97543c916
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/pcie.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_METEORLAKE_PCIE_H__
+#define __SOC_METEORLAKE_PCIE_H__
+
+#include <intelblocks/pcie_rp.h>
+
+const struct pcie_rp_group *get_pcie_rp_table(void);
+
+#endif /* __SOC_METEORLAKE_PCIE_H__ */
diff --git a/src/soc/intel/meteorlake/include/soc/ramstage.h b/src/soc/intel/meteorlake/include/soc/ramstage.h
new file mode 100644
index 0000000000..8f40f46b23
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/ramstage.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <soc/soc_chip.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params);
+void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config);
+void soc_init_pre_device(void *chip_info);
+
+#endif
diff --git a/src/soc/intel/meteorlake/include/soc/serialio.h b/src/soc/intel/meteorlake/include/soc/serialio.h
new file mode 100644
index 0000000000..d34164c620
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/serialio.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SERIALIO_H_
+#define _SERIALIO_H_
+
+enum {
+	PchSerialIoDisabled,
+	PchSerialIoPci,
+	PchSerialIoHidden,
+	PchSerialIoLegacyUart,
+	PchSerialIoSkipInit
+};
+
+enum {
+	PchSerialIoIndexI2C0,
+	PchSerialIoIndexI2C1,
+	PchSerialIoIndexI2C2,
+	PchSerialIoIndexI2C3,
+	PchSerialIoIndexI2C4,
+	PchSerialIoIndexI2C5
+};
+
+enum {
+	PchSerialIoIndexGSPI0,
+	PchSerialIoIndexGSPI1,
+	PchSerialIoIndexGSPI2,
+};
+
+enum {
+	PchSerialIoIndexUART0,
+	PchSerialIoIndexUART1,
+	PchSerialIoIndexUART2
+};
+
+#endif
diff --git a/src/soc/intel/meteorlake/include/soc/soc_info.h b/src/soc/intel/meteorlake/include/soc/soc_info.h
new file mode 100644
index 0000000000..99ab1b5888
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/soc_info.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+uint8_t get_max_usb20_port(void);
+uint8_t get_max_usb30_port(void);
+uint8_t get_max_tcss_port(void);
+uint8_t get_max_tbt_pcie_port(void);
+uint8_t get_max_pcie_port(void);
+uint8_t get_max_pcie_clock(void);
+uint8_t get_max_uart_port(void);
+uint8_t get_max_i2c_port(void);
+uint8_t get_max_gspi_port(void);
diff --git a/src/soc/intel/meteorlake/include/soc/tcss.h b/src/soc/intel/meteorlake/include/soc/tcss.h
new file mode 100644
index 0000000000..014e3076e6
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/tcss.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _SOC_TCSS_H_
+#define _SOC_TCSS_H_
+
+/* Thunderbolt firmware IMR status */
+#define IOM_CSME_IMR_TBT_STATUS			0x14
+#define TBT_VALID_AUTHENTICATION		(1 << 30)
+
+/* IOM aux bias control registers in REGBAR MMIO space */
+#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0	0x1070
+#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(x)	(IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 + (x) * 4)
+#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0	0x1088
+#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x)	(IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4)
+
+#endif /* _SOC_TCSS_H_ */
diff --git a/src/soc/intel/meteorlake/include/soc/usb.h b/src/soc/intel/meteorlake/include/soc/usb.h
new file mode 100644
index 0000000000..e339c7261e
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/usb.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_USB_H_
+#define _SOC_USB_H_
+
+#include <stdint.h>
+
+/* Per Port HS Transmitter Emphasis */
+#define USB2_EMP_OFF			0
+#define USB2_DE_EMP_ON			1
+#define USB2_PRE_EMP_ON			2
+#define USB2_DE_EMP_ON_PRE_EMP_ON	3
+
+/* Per Port Half Bit Pre-emphasis */
+#define USB2_FULL_BIT_PRE_EMP	0
+#define USB2_HALF_BIT_PRE_EMP	1
+
+/* Per Port HS Preemphasis Bias */
+#define USB2_BIAS_0MV		0
+#define USB2_BIAS_11P25MV	1
+#define USB2_BIAS_16P9MV	2
+#define USB2_BIAS_28P15MV	3
+#define USB2_BIAS_39P35MV	5
+#define USB2_BIAS_45MV		6
+#define USB2_BIAS_56P3MV	7
+
+struct usb2_port_config {
+	uint8_t enable;
+	uint8_t ocpin;
+	uint8_t tx_bias;
+	uint8_t tx_emp_enable;
+	uint8_t pre_emp_bias;
+	uint8_t pre_emp_bit;
+};
+
+/* USB Overcurrent pins definition */
+enum {
+	OC0 = 0,
+	OC1,
+	OC2,
+	OC3,
+	OC4,
+	OC5,
+	OC6,
+	OC7,
+	OCMAX,
+	OC_SKIP = 0xff, /* Skip OC programming */
+};
+
+/* Standard USB Port based on length:
+ * - External
+ * - Back Panel
+ * - OTG
+ * - M.2
+ * - Internal device down */
+
+#define USB2_PORT_EMPTY { \
+	.enable        = 0, \
+	.ocpin         = OC_SKIP, \
+	.tx_bias       = USB2_BIAS_0MV, \
+	.tx_emp_enable = USB2_EMP_OFF, \
+	.pre_emp_bias  = USB2_BIAS_0MV, \
+	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Length = 11.5"-12" */
+#define USB2_PORT_LONG(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_39P35MV, \
+	.tx_emp_enable = USB2_PRE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_56P3MV, \
+	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Length  = 6"-11.49" */
+#define USB2_PORT_MID(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_0MV, \
+	.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_45MV, \
+	.pre_emp_bit   = USB2_FULL_BIT_PRE_EMP, \
+}
+
+/* Length = 3"-5.99" */
+#define USB2_PORT_SHORT(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_39P35MV, \
+	.tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_39P35MV, \
+	.pre_emp_bit   = USB2_FULL_BIT_PRE_EMP, \
+}
+
+/* Max TX and Pre-emp settings */
+#define USB2_PORT_MAX(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_56P3MV, \
+	.tx_emp_enable = USB2_PRE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_56P3MV, \
+	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Type-C Port, no BC1.2 charge detect module / MUX
+ * Length  = 3.0" - 9.00" */
+#define USB2_PORT_TYPE_C(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_0MV, \
+	.tx_emp_enable = USB2_PRE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_56P3MV, \
+	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+}
+
+struct usb3_port_config {
+	uint8_t enable;
+	uint8_t ocpin;
+	uint8_t tx_de_emp;
+	uint8_t tx_downscale_amp;
+};
+
+#define USB3_PORT_EMPTY { \
+	.enable           = 0, \
+	.ocpin            = OC_SKIP, \
+	.tx_de_emp        = 0x00, \
+	.tx_downscale_amp = 0x00, \
+}
+
+#define USB3_PORT_DEFAULT(pin) { \
+	.enable           = 1, \
+	.ocpin            = (pin), \
+	.tx_de_emp        = 0x0, \
+	.tx_downscale_amp = 0x00, \
+}
+
+struct tcss_port_config {
+	uint8_t enable;
+	uint8_t ocpin;
+};
+
+#define TCSS_PORT_EMPTY { \
+	.enable           = 0, \
+	.ocpin            = OC_SKIP, \
+}
+
+#define TCSS_PORT_DEFAULT(pin) { \
+	.enable           = 1, \
+	.ocpin            = (pin), \
+}
+
+
+#endif