summaryrefslogtreecommitdiff
path: root/src/soc/intel/meteorlake/chip.c
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2022-07-16 12:37:38 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-07-18 15:38:14 +0000
commitc7c746c3b2cab52a80719bba39cbdc9ea4babb35 (patch)
tree4cd74dcf44391337949b254f49040828b002b35f /src/soc/intel/meteorlake/chip.c
parent10cd06b1c75e4bc69a1de7e3a70c28ff2e5195fc (diff)
soc/intel/meteorlake: Account for GSPI2 everywhere
Commit e54a8fd43247d767f16a37f3e3150b2915d809bc (soc/intel/meteorlake: Add entry for GSPI2 device) added an entry for the GSPI2 device in the devicetree, but did not add any other entries. Ensure that the rest of the code is aware of the GSPI2 device to avoid any problems. Change-Id: Ib59bd289751bd96402c4adc61ffbee3bebe0edb0 Found-by: Coverity CID 1490681 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
Diffstat (limited to 'src/soc/intel/meteorlake/chip.c')
-rw-r--r--src/soc/intel/meteorlake/chip.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c
index 8139b5b3af..5b62c069da 100644
--- a/src/soc/intel/meteorlake/chip.c
+++ b/src/soc/intel/meteorlake/chip.c
@@ -101,6 +101,7 @@ const char *soc_acpi_name(const struct device *dev)
case PCI_DEVFN_UART2: return "UAR2";
case PCI_DEVFN_GSPI0: return "SPI0";
case PCI_DEVFN_GSPI1: return "SPI1";
+ case PCI_DEVFN_GSPI2: return "SPI2";
/* Keeping ACPI device name coherent with ec.asl */
case PCI_DEVFN_ESPI: return "LPCB";
case PCI_DEVFN_HDA: return "HDAS";