diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 18:46:44 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-21 06:41:09 +0000 |
| commit | d9802111122d6273c711eccd352d29d7f34ba4e2 (patch) | |
| tree | c98f9aff4f07069b4fa72f74dcba48cf06514a70 /src/soc/intel/fsp_baytrail/include | |
| parent | eb5147027e974ba365aa4706935c7c9582cf7619 (diff) | |
soc/intel/fsp_baytrail: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I0b0344f1ebed12207a77c985f27893a1353c0925
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/include')
22 files changed, 0 insertions, 2391 deletions
diff --git a/src/soc/intel/fsp_baytrail/include/soc/acpi.h b/src/soc/intel/fsp_baytrail/include/soc/acpi.h deleted file mode 100644 index 917419e4df..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/acpi.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_ACPI_H_ -#define _BAYTRAIL_ACPI_H_ - -#include <arch/acpi.h> -#include <soc/nvs.h> -#include <device/device.h> - -void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); -unsigned long acpi_madt_irq_overrides(unsigned long current); -void acpi_init_gnvs(global_nvs_t *gnvs); - -#ifndef __SIMPLE_DEVICE__ -unsigned long southcluster_write_acpi_tables(struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp); -void southcluster_inject_dsdt(struct device *device); -#endif - -#endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h deleted file mode 100644 index de902aac6f..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_INTEL_FSP_BAYTRAIL_BAYTRAIL_H__ -#define __SOC_INTEL_FSP_BAYTRAIL_BAYTRAIL_H__ - -#define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS -#define CPU_MICROCODE_CBFS_LEN 0x26000 - -/* Southbridge internal device IO BARs (Set to match FSP settings) */ -#define SMBUS_IO_BASE 0xefa0 -#define SMBUS_SLAVE_ADDR 0x24 -#define DEFAULT_GPIOBASE 0x0500 -#define DEFAULT_ABASE 0x0400 - -/* Southbridge internal device MEM BARs (Set to match FSP settings) */ -#define DEFAULT_IBASE 0xfed08000 -#define DEFAULT_PBASE 0xfed03000 -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif - -/* Device 0:0.0 PCI configuration space (Host Bridge) */ -#define SKPAD 0xFC - -/* SOC types */ -#define SOC_TYPE_BAYTRAIL 0x0F1C - -/* Everything below this line is ignored in the DSDT */ -#ifndef __ACPI__ -#ifndef __ASSEMBLER__ -#include <device/device.h> - -int bridge_silicon_revision(void); -void rangeley_early_initialization(void); -void set_max_freq(void); - -/* soc.c */ -int soc_silicon_revision(void); -int soc_silicon_type(void); -int soc_silicon_supported(int type, int rev); -void soc_enable(struct device *dev); - -void report_platform_info(void); - -#endif /* __ASSEMBLER__ */ -#endif /* __ACPI__ */ - -#endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h deleted file mode 100644 index ec1e568bfd..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_DEVICE_NVS_H_ -#define _BAYTRAIL_DEVICE_NVS_H_ - -#include <stdint.h> - -#define LPSS_NVS_SIO_DMA1 0 -#define LPSS_NVS_I2C1 1 -#define LPSS_NVS_I2C2 2 -#define LPSS_NVS_I2C3 3 -#define LPSS_NVS_I2C4 4 -#define LPSS_NVS_I2C5 5 -#define LPSS_NVS_I2C6 6 -#define LPSS_NVS_I2C7 7 -#define LPSS_NVS_SIO_DMA2 8 -#define LPSS_NVS_SPI 9 -#define LPSS_NVS_PWM1 10 -#define LPSS_NVS_PWM2 11 -#define LPSS_NVS_HSUART1 12 -#define LPSS_NVS_HSUART2 13 - -#define SCC_NVS_MMC 0 -#define SCC_NVS_SDIO 1 -#define SCC_NVS_SD 2 - -typedef struct { - /* Device Enabled in ACPI Mode */ - u8 lpss_en[14]; - u8 scc_en[3]; - u8 lpe_en; - - /* BAR 0 */ - u32 lpss_bar0[14]; - u32 scc_bar0[3]; - u32 lpe_bar0; - - /* BAR 1 */ - u32 lpss_bar1[14]; - u32 scc_bar1[3]; - u32 lpe_bar1; - - /* Extra */ - u32 lpe_fw; /* LPE Firmware */ - u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ -} __packed device_nvs_t; - -#endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/ehci.h b/src/soc/intel/fsp_baytrail/include/soc/ehci.h deleted file mode 100644 index fe990b7017..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/ehci.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef BAYTRAIL_EHCI_H -#define BAYTRAIL_EHCI_H - -/* EHCI PCI Registers */ -#define EHCI_CMD_STS 0x04 -# define INTRDIS (1 << 10) -#define EHCI_SBRN_FLA_PWC 0x60 -# define PORTWKIMP (1 << 16) -# define PORTWKCAPMASK (0x3ff << 17) -#define EHCI_USB2PDO 0x64 - -/* EHCI Memory Registers */ -#define USB2CMD 0x20 -# define USB2CMD_ASE (1 << 5) -# define USB2CMD_PSE (1 << 4) -# define USB2CMD_HCRESET (1 << 1) -# define USB2CMD_RS (1 << 0) -#define USB2STS 0x24 -# define USB2STS_HCHALT (1 << 12) - -/* RCBA EHCI Registers */ -#define RCBA_FUNC_DIS 0x220 -# define RCBA_EHCI_DIS (1 << 0) - -#endif /* BAYTRAIL_EHCI_H */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/gfx.h b/src/soc/intel/fsp_baytrail/include/soc/gfx.h deleted file mode 100644 index e7fc8ca604..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/gfx.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_GFX_H_ -#define _BAYTRAIL_GFX_H_ - -/* - * PCI config registers. - */ - -#define GGC 0x50 -# define GGC_VGA_DISABLE (1 << 1) -# define GGC_GTT_SIZE_MASK (3 << 8) -# define GGC_GTT_SIZE_0MB (0 << 8) -# define GGC_GTT_SIZE_1MB (1 << 8) -# define GGC_GTT_SIZE_2MB (2 << 8) -# define GGC_GSM_SIZE_MASK (0x1f << 3) -# define GGC_GSM_SIZE_0MB (0 << 3) -# define GGC_GSM_SIZE_32MB (1 << 3) -# define GGC_GSM_SIZE_64MB (2 << 3) -# define GGC_GSM_SIZE_128MB (4 << 3) - -#define GSM_BASE 0x5c -#define GTT_BASE 0x70 - -#define MSAC 0x62 -#define APERTURE_SIZE_MASK (3 << 1) -#define APERTURE_SIZE_128MB (0 << 1) -#define APERTURE_SIZE_256MB (1 << 1) -#define APERTURE_SIZE_512MB (3 << 1) - -#endif /* _BAYTRAIL_GFX_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h deleted file mode 100644 index 137ec95f14..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h +++ /dev/null @@ -1,442 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_GPIO_H_ -#define _BAYTRAIL_GPIO_H_ - -#include <stdint.h> -#include <device/mmio.h> -#include <soc/iomap.h> - -/* #define GPIO_DEBUG */ - -/* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */ -#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE) -#define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE) -#define GPSSUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS) - -/* DIRQ registers start at pad base + 0x980 */ -#define PAD_BASE_DIRQ_OFFSET 0x980 - -/* Pad register offset */ -#define PAD_CONF0_REG 0x0 -#define PAD_CONF1_REG 0x4 -#define PAD_VAL_REG 0x8 - -/* Legacy IO register base */ -#define GPSCORE_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x00) -#define GPSSUS_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x80) -/* Some banks have no legacy GPIO interface */ -#define GP_LEGACY_BASE_NONE 0xFFFF - -#define LEGACY_USE_SEL_REG 0x00 -#define LEGACY_IO_SEL_REG 0x04 -#define LEGACY_GP_LVL_REG 0x08 -#define LEGACY_TPE_REG 0x0C -#define LEGACY_TNE_REG 0x10 -#define LEGACY_TS_REG 0x14 -#define LEGACY_WAKE_EN_REG 0x18 - -/* Number of GPIOs in each bank */ -#define GPNCORE_COUNT 27 -#define GPSCORE_COUNT 102 -#define GPSSUS_COUNT 44 - -/* GPIO legacy IO register settings */ -#define GPIO_USE_MMIO 0 -#define GPIO_USE_LEGACY 1 - -#define GPIO_DIR_OUTPUT 0 -#define GPIO_DIR_INPUT 1 - -#define GPIO_LEVEL_LOW 0 -#define GPIO_LEVEL_HIGH 1 - -#define GPIO_PEDGE_DISABLE 0 -#define GPIO_PEDGE_ENABLE 1 - -#define GPIO_NEDGE_DISABLE 0 -#define GPIO_NEDGE_ENABLE 1 - -/* config0[29] - Disable second mask */ -#define PAD_MASK2_DISABLE (1 << 29) - -/* config0[27] - Direct Irq En */ -#define PAD_IRQ_EN (1 << 27) - -/* config0[26] - gd_tne */ -#define PAD_TNE_IRQ (1 << 26) - -/* config0[25] - gd_tpe */ -#define PAD_TPE_IRQ (1 << 25) - -/* config0[24] - Gd Level */ -#define PAD_LEVEL_IRQ (1 << 24) -#define PAD_EDGE_IRQ (0 << 24) - -/* config0[17] - Slow clkgate / glitch filter */ -#define PAD_SLOWGF_ENABLE (1 << 17) - -/* config0[16] - Fast clkgate / glitch filter */ -#define PAD_FASTGF_ENABLE (1 << 16) - -/* config0[15] - Hysteresis enable (inverted) */ -#define PAD_HYST_DISABLE (1 << 15) -#define PAD_HYST_ENABLE (0 << 15) - -/* config0[14:13] - Hysteresis control */ -#define PAD_HYST_CTRL_DEFAULT (2 << 13) - -/* config0[11] - Bypass Flop */ -#define PAD_FLOP_BYPASS (1 << 11) -#define PAD_FLOP_ENABLE (0 << 11) - -/* config0[10:9] - Pull str */ -#define PAD_PU_2K (0 << 9) -#define PAD_PU_10K (1 << 9) -#define PAD_PU_20K (2 << 9) -#define PAD_PU_40K (3 << 9) - -/* config0[8:7] - Pull assign */ -#define PAD_PULL_DISABLE (0 << 7) -#define PAD_PULL_UP (1 << 7) -#define PAD_PULL_DOWN (2 << 7) - -/* config0[2:0] - Func. pin mux */ -#define PAD_FUNC0 0x0 -#define PAD_FUNC1 0x1 -#define PAD_FUNC2 0x2 -#define PAD_FUNC3 0x3 -#define PAD_FUNC4 0x4 -#define PAD_FUNC5 0x5 -#define PAD_FUNC6 0x6 - -/* pad config0 power-on values - We will not often want to change these */ -#define PAD_CONFIG0_DEFAULT (PAD_MASK2_DISABLE | PAD_SLOWGF_ENABLE | \ - PAD_FASTGF_ENABLE | PAD_HYST_DISABLE | \ - PAD_HYST_CTRL_DEFAULT | PAD_FLOP_BYPASS) - -/* pad config1 reg power-on values - Shouldn't need to change this */ -#define PAD_CONFIG1_DEFAULT 0x8000 - -/* pad_val[2] - Iinenb - active low */ -#define PAD_VAL_INPUT_DISABLE (1 << 2) -#define PAD_VAL_INPUT_ENABLE (0 << 2) - -/* pad_val[1] - Ioutenb - active low */ -#define PAD_VAL_OUTPUT_DISABLE (1 << 1) -#define PAD_VAL_OUTPUT_ENABLE (0 << 1) - -/* Input / Output state should usually be mutually exclusive */ -#define PAD_VAL_INPUT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) -#define PAD_VAL_OUTPUT (PAD_VAL_OUTPUT_ENABLE | PAD_VAL_INPUT_DISABLE) - -/* pad_val[0] - Value */ -#define PAD_VAL_HIGH (1 << 0) -#define PAD_VAL_LOW (0 << 0) - -/* pad_val reg power-on default varies by pad, and apparently can cause issues - * if not set correctly, even if the pin isn't configured as GPIO. */ -#define PAD_VAL_DEFAULT PAD_VAL_INPUT - -/* Configure GPIOs as MMIO by default */ -#define GPIO_INPUT_PU_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_PD_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_PU_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_PD_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_NOPU \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_LEGACY_NOPU \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .is_gpio = 1 } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -#define GPIO_OUT_LOW_LEGACY \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_LOW, \ - .is_gpio = 1 } - -#define GPIO_OUT_HIGH_LEGACY \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_HIGH, \ - .is_gpio = 1 } - -#define GPIO_OUT_LOW \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ - .use_sel = GPIO_USE_MMIO, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_LOW, \ - .is_gpio = 1 } - -#define GPIO_OUT_HIGH \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ - .use_sel = GPIO_USE_MMIO, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_HIGH, \ - .is_gpio = 1 } - -/* Define no-pull / PU / PD configs for each functional config option */ -#define GPIO_FUNC(_func, _pudir, _str) \ - { .use_sel = GPIO_USE_MMIO, \ - .pad_conf0 = PAD_FUNC##_func | PAD_##_pudir | PAD_PU_##_str | \ - PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } - -/* Default functional configs -- no PU */ -#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 20K) -#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 20K) -#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 20K) -#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 20K) -#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 20K) -#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 20K) -#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 20K) - -/* ACPI GPIO routing. Assume everything is externally pulled and negative edge - * triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */ -#define GPIO_ACPI_SCI \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = 1, \ - .sci = 1, \ - .wake_en = 1, } -#define GPIO_ACPI_WAKE \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = 1, \ - .wake_en = 1, } -#define GPIO_ACPI_SMI \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = 1, \ - .smi = 1} - -/* End marker */ -#define GPIO_LIST_END 0xffffffff - -#define GPIO_END \ - { .pad_conf0 = GPIO_LIST_END } - -/* Common default GPIO settings */ -#define GPIO_INPUT GPIO_INPUT_NOPU -#define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU -#define GPIO_INPUT_PU GPIO_INPUT_PU_20K -#define GPIO_INPUT_PD GPIO_INPUT_PD_20K -#define GPIO_NC GPIO_INPUT_PU_20K -#define GPIO_DEFAULT GPIO_FUNC0 - -/* 16 DirectIRQs per supported bank */ -#define GPIO_MAX_DIRQS 16 - -/* Most pins are GPIO function 0. Some banks have a range of pins with GPIO - * function 1. Indicate first / last GPIOs with function 1. */ -#define GPIO_NONE 255 -/* All NCORE GPIOs are function 0 */ -#define GPNCORE_GPIO_F1_RANGE_START GPIO_NONE -#define GPNCORE_GPIO_F1_RANGE_END GPIO_NONE -/* SCORE GPIO [92:93] are function 1 */ -#define GPSCORE_GPIO_F1_RANGE_START 92 -#define GPSCORE_GPIO_F1_RANGE_END 93 -/* SSUS GPIO [11:21] are function 1 */ -#define GPSSUS_GPIO_F1_RANGE_START 11 -#define GPSSUS_GPIO_F1_RANGE_END 21 - -struct soc_gpio_map { - u32 pad_conf0; - u32 pad_conf1; - u32 pad_val; - u32 use_sel : 1; - u32 io_sel : 1; - u32 gp_lvl : 1; - u32 tpe : 1; - u32 tne : 1; - u32 wake_en : 1; - u32 smi : 1; - u32 is_gpio : 1; - u32 sci : 1; -} __packed; - -struct soc_gpio_config { - const struct soc_gpio_map *ncore; - const struct soc_gpio_map *score; - const struct soc_gpio_map *ssus; - const u8 (*core_dirq)[GPIO_MAX_DIRQS]; - const u8 (*sus_dirq)[GPIO_MAX_DIRQS]; -}; - -/* Description of GPIO 'bank' ex. {ncore, score. ssus} */ -struct gpio_bank { - const int gpio_count; - const u8 *gpio_to_pad; - const int legacy_base; - const unsigned long pad_base; - const u8 has_wake_en :1; - const u8 gpio_f1_range_start; - const u8 gpio_f1_range_end; -}; - -void smm_southcluster_save_gpio_route(uint32_t route); -void setup_soc_gpios(struct soc_gpio_config *config); -/* This function is weak and can be overridden by a mainboard function. */ -struct soc_gpio_config* mainboard_get_gpios(void); -uint8_t read_score_gpio(uint8_t gpio_num); -void write_score_gpio(uint8_t gpio_num, uint8_t val); -uint8_t read_ssus_gpio(uint8_t gpio_num); -void write_ssus_gpio(uint8_t gpio_num, uint8_t val); -void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val); -void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val); - -/* Functions / defines for changing GPIOs in romstage */ -/* SCORE Pad definitions. */ -#define UART_RXD_PAD 82 -#define UART_TXD_PAD 83 -#define PCU_SMB_CLK_PAD 88 -#define PCU_SMB_DATA_PAD 90 - -static inline uint32_t *score_pconf0(int pad_num) -{ - return (uint32_t *)(GPSCORE_PAD_BASE + pad_num * 16); -} - -static inline uint32_t *ssus_pconf0(int pad_num) -{ - return (uint32_t *)(GPSSUS_PAD_BASE + pad_num * 16); -} - -static inline void score_select_func(int pad, int func) -{ - uint32_t reg; - uint32_t *pconf0_addr = score_pconf0(pad); - - reg = read32(pconf0_addr); - reg &= ~0x7; - reg |= func & 0x7; - write32(pconf0_addr, reg); -} - -static inline void ssus_select_func(int pad, int func) -{ - uint32_t reg; - uint32_t *pconf0_addr = ssus_pconf0(pad); - - reg = read32(pconf0_addr); - reg &= ~0x7; - reg |= func & 0x7; - write32(pconf0_addr, reg); -} - - -/* These functions require that the input pad be configured as an input GPIO */ -static inline int score_get_gpio(int pad) -{ - uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - return read32(val_addr) & PAD_VAL_HIGH; -} - -static inline int ssus_get_gpio(int pad) -{ - uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - return read32(val_addr) & PAD_VAL_HIGH; -} - -/* These functions require that the output pad is configured as an output */ -/* GPIO and is mapped to memory space and not IO space. */ -static inline void score_set_gpio(int pad, int val) -{ - uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - write32(val_addr, ((read32(val_addr) & ~0x1) | val)); -} - -static inline void ssus_set_gpio(int pad, int val) -{ - uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - write32(val_addr, ((read32(val_addr) & ~0x1) | val)); -} - -static inline void ssus_disable_internal_pull(int pad) -{ - uint32_t reg; - uint32_t *pconf0_addr = ssus_pconf0(pad); - - reg = read32(pconf0_addr); - reg &= ~(0xf << 7); - write32(pconf0_addr, reg); -} - -#endif /* _BAYTRAIL_GPIO_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/i2c.h b/src/soc/intel/fsp_baytrail/include/soc/i2c.h deleted file mode 100644 index 3a4ff2c32b..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/i2c.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014-2019 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ -#define __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ - -#define I2C_SOFTWARE_RESET 0x804 -#define I2C_RESET_APB (1 << 1) -#define I2C_RESET_FUNC (1 << 0) - -#endif /* __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/iomap.h b/src/soc/intel/fsp_baytrail/include/soc/iomap.h deleted file mode 100644 index d54d3fcc29..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/iomap.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_IOMAP_H_ -#define _BAYTRAIL_IOMAP_H_ - -/* - * Memory Mapped IO bases. - */ - -/* PCI Configuration Space */ -#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MCFG_BASE_SIZE 0x10000000 - -/* Transactions in this range will abort */ -#define ABORT_BASE_ADDRESS 0xfeb00000 -#define ABORT_BASE_SIZE 0x00100000 - -/* Power Management Controller */ -#define PMC_BASE_ADDRESS 0xfed03000 -#define PMC_BASE_SIZE 0x400 - -/* IO Memory */ -#define IO_BASE_ADDRESS 0xfed0c000 -#define IO_BASE_OFFSET_GPSCORE 0x0000 -#define IO_BASE_OFFSET_GPNCORE 0x1000 -#define IO_BASE_OFFSET_GPSSUS 0x2000 -#define IO_BASE_SIZE 0x4000 - -/* Intel Legacy Block */ -#define ILB_BASE_ADDRESS 0xfed08000 -#define ILB_BASE_SIZE 0x400 - -/* SPI Bus */ -#define SPI_BASE_ADDRESS 0xfed01000 -#define SPI_BASE_SIZE 0x400 - -/* MODPHY */ -#define MPHY_BASE_ADDRESS 0xfef00000 -#define MPHY_BASE_SIZE 0x100000 - -/* Power Management Unit */ -#define PUNIT_BASE_ADDRESS 0xfed05000 -#define PUNIT_BASE_SIZE 0x800 - -/* Root Complex Base Address */ -#define RCBA_BASE_ADDRESS 0xfed1c000 -#define RCBA_BASE_SIZE 0x400 - -/* High Performance Event Timer */ -#define HPET_BASE_ADDRESS 0xfed00000 -#define HPET_BASE_SIZE 0x400 - -/* Temporary Base Address */ -#define TEMP_BASE_ADDRESS 0xfd000000 -#define EARLY_I2C_BASE_ADDRESS 0xfe020000 -#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) - -/* - * IO Port bases. - */ -#define ACPI_BASE_ADDRESS 0x0400 -#define ACPI_BASE_SIZE 0x80 - -#define GPIO_BASE_ADDRESS 0x0500 -#define GPIO_BASE_SIZE 0x100 - -#define SMBUS_BASE_ADDRESS 0xefa0 - -#ifndef __ACPI__ -#include <stdint.h> - -/* Read Top of Low Memory (BMBOUND) */ -uint32_t nc_read_top_of_low_memory(void); -#endif - -#endif /* _BAYTRAIL_IOMAP_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/iosf.h b/src/soc/intel/fsp_baytrail/include/soc/iosf.h deleted file mode 100644 index 0982da68db..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/iosf.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2016 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_IOSF_H_ -#define _BAYTRAIL_IOSF_H_ - -#include <stdint.h> -#include <soc/pci_devs.h> - -/* - * The Bay Trail SoC has a message network called IOSF Sideband. The access - * routines are through 3 registers in PCI config space of 00:00.0: - * MCR - control register - * MDR - data register - * MCRX - control register extension - * The extension register is only used for addresses that don't fit into the - * 8 bit register address. - */ - -#ifndef PCI_DEV -#define PCI_DEV(SEGBUS, DEV, FN) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12)) -#endif -#define IOSF_PCI_DEV PCI_DEV(0,SOC_DEV,SOC_FUNC) - -#define MCR_REG 0xd0 -#define IOSF_OPCODE(x) ((x) << 24) -#define IOSF_PORT(x) ((0xff & (x)) << 16) -#define IOSF_REG(x) ((0xff & (x)) << 8) -#define IOSF_REG_UPPER(x) (((~0xff) & (x))) -#define IOSF_BYTE_EN_0 0x10 -#define IOSF_BYTE_EN_1 0x20 -#define IOSF_BYTE_EN_2 0x40 -#define IOSF_BYTE_EN_3 0x80 -#define IOSF_BYTE_EN \ - (IOSF_BYTE_EN_0 | IOSF_BYTE_EN_1 | IOSF_BYTE_EN_2 | IOSF_BYTE_EN_3) -#define MDR_REG 0xd4 -#define MCRX_REG 0xd8 - -uint32_t iosf_aunit_read(int reg); -void iosf_aunit_write(int reg, uint32_t val); -uint32_t iosf_cpu_bus_read(int reg); -void iosf_cpu_bus_write(int reg, uint32_t val); -uint32_t iosf_bunit_read(int reg); -void iosf_bunit_write(int reg, uint32_t val); -uint32_t iosf_dunit_read(int reg); -void iosf_dunit_write(int reg, uint32_t val); -/* Some registers are per channel while the globals live in dunit 0 */ -uint32_t iosf_dunit_ch0_read(int reg); -uint32_t iosf_dunit_ch1_read(int reg); -uint32_t iosf_punit_read(int reg); -void iosf_punit_write(int reg, uint32_t val); -uint32_t iosf_usbphy_read(int reg); -void iosf_usbphy_write(int reg, uint32_t val); -uint32_t iosf_ushphy_read(int reg); -void iosf_ushphy_write(int reg, uint32_t val); -uint32_t iosf_sec_read(int reg); -void iosf_sec_write(int reg, uint32_t val); -uint32_t iosf_port45_read(int reg); -void iosf_port45_write(int reg, uint32_t val); -uint32_t iosf_port46_read(int reg); -void iosf_port46_write(int reg, uint32_t val); -uint32_t iosf_port47_read(int reg); -void iosf_port47_write(int reg, uint32_t val); -uint32_t iosf_port55_read(int reg); -void iosf_port55_write(int reg, uint32_t val); -uint32_t iosf_port58_read(int reg); -void iosf_port58_write(int reg, uint32_t val); -uint32_t iosf_port59_read(int reg); -void iosf_port59_write(int reg, uint32_t val); -uint32_t iosf_port5a_read(int reg); -void iosf_port5a_write(int reg, uint32_t val); -uint32_t iosf_lpss_read(int reg); -void iosf_lpss_write(int reg, uint32_t val); -uint32_t iosf_ccu_read(int reg); -void iosf_ccu_write(int reg, uint32_t val); -uint32_t iosf_score_read(int reg); -void iosf_score_write(int reg, uint32_t val); -uint32_t iosf_scc_read(int reg); -void iosf_scc_write(int reg, uint32_t val); -uint32_t iosf_porta2_read(int reg); -void iosf_porta2_write(int reg, uint32_t val); -uint32_t iosf_ssus_read(int reg); -void iosf_ssus_write(int reg, uint32_t val); - -/* IOSF ports. */ -#define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ -#define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */ -#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */ -#define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */ -#define IOSF_PORT_BUNIT 0x03 /* System Memory Arbiter/Bunit */ -#define IOSF_PORT_PMC 0x04 /* Power Management Controller */ -#define IOSF_PORT_GFX 0x06 /* Graphics Adapter */ -#define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ -#define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ -#define IOSF_PORT_USBPHY 0x43 /* USB PHY */ -#define IOSF_PORT_SEC 0x44 /* SEC */ -#define IOSF_PORT_0x45 0x45 -#define IOSF_PORT_0x46 0x46 -#define IOSF_PORT_0x47 0x47 -#define IOSF_PORT_SCORE 0x48 /* SCORE */ -#define IOSF_PORT_0x55 0x55 -#define IOSF_PORT_0x58 0x58 -#define IOSF_PORT_0x59 0x59 -#define IOSF_PORT_0x5a 0x5a -#define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ -#define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ -#define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ -#define IOSF_PORT_0xa2 0xa2 -#define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ -#define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ -#define IOSF_PORT_SSUS 0xa8 /* SUS */ -#define IOSF_PORT_CCU 0xa9 /* Clock control unit. */ - -/* Read and write opcodes differ per port. */ -#define IOSF_OP_READ_AUNIT 0x10 -#define IOSF_OP_WRITE_AUNIT (IOSF_OP_READ_AUNIT | 1) -#define IOSF_OP_READ_SYSMEMC 0x10 -#define IOSF_OP_WRITE_SYSMEMC (IOSF_OP_READ_SYSMEMC | 1) -#define IOSF_OP_READ_CPU_BUS 0x10 -#define IOSF_OP_WRITE_CPU_BUS (IOSF_OP_READ_CPU_BUS | 1) -#define IOSF_OP_READ_BUNIT 0x10 -#define IOSF_OP_WRITE_BUNIT (IOSF_OP_READ_BUNIT | 1) -#define IOSF_OP_READ_PMC 0x06 -#define IOSF_OP_WRITE_PMC (IOSF_OP_READ_PMC | 1) -#define IOSF_OP_READ_GFX 0x00 -#define IOSF_OP_WRITE_GFX (IOSF_OP_READ_GFX | 1) -#define IOSF_OP_READ_SYSMEMIO 0x06 -#define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1) -#define IOSF_OP_READ_USBPHY 0x06 -#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) -#define IOSF_OP_READ_SEC 0x04 -#define IOSF_OP_WRITE_SEC (IOSF_OP_READ_SEC | 1) -#define IOSF_OP_READ_0x45 0x06 -#define IOSF_OP_WRITE_0x45 (IOSF_OP_READ_0x45 | 1) -#define IOSF_OP_READ_0x46 0x06 -#define IOSF_OP_WRITE_0x46 (IOSF_OP_READ_0x46 | 1) -#define IOSF_OP_READ_0x47 0x06 -#define IOSF_OP_WRITE_0x47 (IOSF_OP_READ_0x47 | 1) -#define IOSF_OP_READ_SCORE 0x06 -#define IOSF_OP_WRITE_SCORE (IOSF_OP_READ_SCORE | 1) -#define IOSF_OP_READ_0x55 0x04 -#define IOSF_OP_WRITE_0x55 (IOSF_OP_READ_0x55 | 1) -#define IOSF_OP_READ_0x58 0x06 -#define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) -#define IOSF_OP_READ_0x59 0x06 -#define IOSF_OP_WRITE_0x59 (IOSF_OP_READ_0x59 | 1) -#define IOSF_OP_READ_0x5a 0x04 -#define IOSF_OP_WRITE_0x5a (IOSF_OP_READ_0x5a | 1) -#define IOSF_OP_READ_USHPHY 0x06 -#define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) -#define IOSF_OP_READ_SCC 0x06 -#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) -#define IOSF_OP_READ_LPSS 0x06 -#define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1) -#define IOSF_OP_READ_0xa2 0x06 -#define IOSF_OP_WRITE_0xa2 (IOSF_OP_READ_0xa2 | 1) -#define IOSF_OP_READ_SATAPHY 0x00 -#define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) -#define IOSF_OP_READ_PCIEPHY 0x00 -#define IOSF_OP_WRITE_PCIEPHY (IOSF_OP_READ_PCIEPHY | 1) -#define IOSF_OP_READ_SSUS 0x10 -#define IOSF_OP_WRITE_SSUS (IOSF_OP_READ_SSUS | 1) -#define IOSF_OP_READ_CCU 0x06 -#define IOSF_OP_WRITE_CCU (IOSF_OP_READ_CCU | 1) - -/* - * BUNIT Registers. - */ - -#define BNOCACHE 0x23 -/* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */ -#define BUNIT_BMBOUND 0x25 -/* BMBOUND_HI describes the available RAM above 4GiB. It has a - * 256MiB granularity. Physical address bits 35:28 are compared with 31:24 - * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB - * granularity care needs to be taken with the e820 map to account for a hole - * in the RAM. */ -#define BUNIT_BMBOUND_HI 0x26 -#define BUNIT_MMCONF_REG 0x27 -/* The SMMRR registers define the SMM region in MiB granularity. */ -#define BUNIT_SMRCP 0x2b -#define BUNIT_SMRRAC 0x2c -#define BUNIT_SMRWAC 0x2d -#define BUNIT_SMRRL 0x2e -#define BUNIT_SMRRH 0x2f -# define BUNIT_SMRR_ENABLE (1 << 31) - -/* SA ID bits. */ -#define SAI_IA_UNTRUSTED (1 << 0) -#define SAI_IA_SMM (1 << 2) -#define SAI_IA_BOOT (1 << 4) - -/* - * DUNIT Registers. - */ - -#define DRP 0x00 -# define DRP_DIMM0_RANK0_EN (0x01 << 0) -# define DRP_DIMM0_RANK1_EN (0x01 << 1) -# define DRP_DIMM1_RANK0_EN (0x01 << 2) -# define DRP_DIMM1_RANK1_EN (0x01 << 3) -# define DRP_RANK_MASK (DRP_DIMM0_RANK0_EN | DRP_DIMM0_RANK1_EN | \ - DRP_DIMM1_RANK0_EN | DRP_DIMM1_RANK1_EN) -#define DTR0 0x01 -# define DTR0_SPEED_MASK 0x03 -# define DTR0_SPEED_800 0x00 -# define DTR0_SPEED_1066 0x01 -# define DTR0_SPEED_1333 0x02 -# define DTR0_SPEED_1600 0x03 - -/* - * PUNIT Registers - */ -#define SB_BIOS_CONFIG 0x06 -# define SB_BIOS_CONFIG_ECC_EN (1 << 31) -# define SB_BIOS_CONFIG_DUAL_CH_DIS (1 << 30) -# define SB_BIOS_CONFIG_EFF_ECC (1 << 29) -# define SB_BIOS_CONFIG_EFF_DUAL_CH_DIS (1 << 28) -# define SB_BIOS_CONFIG_PERF_MODE (1 << 17) -# define SB_BIOS_CONFIG_PDM_MODE (1 << 16) -# define SB_BIOS_CONFIG_DDRIO_PWRGATE (1 << 8) -# define SB_BIOS_CONFIG_GFX_TURBO_DIS (1 << 7) -# define SB_BIOS_CONFIG_PS2_EN_VNN (1 << 3) -# define SB_BIOS_CONFIG_PS2_EN_VCC (1 << 2) -# define SB_BIOS_CONFIG_PCIE_PLLOFFOK (1 << 1) -# define SB_BIOS_CONFIG_USB_CACHING_EN (1 << 0) -#define BIOS_RESET_CPL 0x05 -# define BIOS_RESET_CPL_ALL_DONE (1 << 1) -# define BIOS_RESET_CPL_RESET_DONE (1 << 0) -#define PUNIT_PWRGT_CONTROL 0x60 -#define PUNIT_PWRGT_STATUS 0x61 -#define PUNIT_GPU_EC_VIRUS 0xd2 - -#define PUNIT_SOC_POWER_BUDGET 0x02 -#define PUNIT_SOC_ENERGY_CREDIT 0x03 -#define PUNIT_PTMC 0x80 -#define PUNIT_GFXT 0x88 -#define PUNIT_VEDT 0x89 -#define PUNIT_ISPT 0x8c -#define PUNIT_PTPS 0xb2 -#define PUNIT_TE_AUX0 0xb5 -#define PUNIT_TE_AUX1 0xb6 -#define PUNIT_TE_AUX2 0xb7 -#define PUNIT_TE_AUX3 0xb8 -#define PUNIT_TTE_VRIccMax 0xb9 -#define PUNIT_TTE_VRHot 0xba -#define PUNIT_TTE_XXPROCHOT 0xbb -#define PUNIT_TTE_SLM0 0xbc -#define PUNIT_TTE_SLM1 0xbd -#define PUNIT_TTE_SWT 0xbf - -/* - * LPSS Registers - */ -#define LPSS_SIO_DMA1_CTL 0x280 -#define LPSS_I2C1_CTL 0x288 -#define LPSS_I2C2_CTL 0x290 -#define LPSS_I2C3_CTL 0x298 -#define LPSS_I2C4_CTL 0x2a0 -#define LPSS_I2C5_CTL 0x2a8 -#define LPSS_I2C6_CTL 0x2b0 -#define LPSS_I2C7_CTL 0x2b8 -#define LPSS_SIO_DMA2_CTL 0x240 -#define LPSS_PWM1_CTL 0x248 -#define LPSS_PWM2_CTL 0x250 -#define LPSS_HSUART1_CTL 0x258 -#define LPSS_HSUART2_CTL 0x260 -#define LPSS_SPI_CTL 0x268 -# define LPSS_CTL_ACPI_INT_EN (1 << 21) -# define LPSS_CTL_PCI_CFG_DIS (1 << 20) -# define LPSS_CTL_SNOOP (1 << 18) -# define LPSS_CTL_NOSNOOP (1 << 19) -# define LPSS_CTL_PM_CAP_PRSNT (1 << 1) - -/* - * SCC Registers - */ -#define SCC_SD_CTL 0x504 -#define SCC_SDIO_CTL 0x508 -#define SCC_MMC_CTL 0x50c -# define SCC_CTL_PCI_CFG_DIS (1 << 0) -# define SCC_CTL_ACPI_INT_EN (1 << 1) - -/* - * CCU Registers - */ - -#define PLT_CLK_CTRL_0 0x3c -#define PLT_CLK_CTRL_1 0x40 -#define PLT_CLK_CTRL_2 0x44 -#define PLT_CLK_CTRL_3 0x48 -#define PLT_CLK_CTRL_4 0x4c -#define PLT_CLK_CTRL_5 0x50 -# define PLT_CLK_CTRL_19P2MHZ_FREQ (0 << 1) -# define PLT_CLK_CTRL_25MHZ_FREQ (1 << 1) -# define PLT_CLK_CTRL_SELECT_FREQ (1 << 0) - -/* - * USBPHY Registers - */ -#define USBPHY_COMPBG 0x7f04 -#define USBPHY_PER_PORT_LANE0 0x4100 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP0 0x4122 -#define USBPHY_PER_PORT_LANE1 0x4200 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP1 0x4222 -#define USBPHY_PER_PORT_LANE2 0x4300 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP2 0x4322 -#define USBPHY_PER_PORT_LANE3 0x4400 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP3 0x4422 - -/* - * USHPHY Registers - */ -#define USHPHY_CDN_PLL_CONTROL 0x03c0 -#define USHPHY_CDN_VCO_START_CAL_POINT 0x0054 -#define USHPHY_CCDRLF 0x8040 -#define USHPHY_PEAKING_AMP_CONFIG_DIAG 0x80a8 -#define USHPHY_OFFSET_COR_CONFIG_DIAG 0x80b0 -#define USHPHY_VGA_GAIN_CONFIG_DIAG 0x8080 -#define USHPHY_REE_DAC_CONTROL 0x80b8 -#define USHPHY_CDN_U1_POWER_STATE_DEF 0x0000 - -/* - * LPE Registers - */ -#define LPE_PCICFGCTR1 0x0500 -# define LPE_PCICFGCTR1_PCI_CFG_DIS (1 << 0) -# define LPE_PCICFGCTR1_ACPI_INT_EN (1 << 1) - -#endif /* _BAYTRAIL_IOSF_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/irq.h b/src/soc/intel/fsp_baytrail/include/soc/irq.h deleted file mode 100644 index de8fc03cde..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/irq.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_IRQ_H_ -#define _BAYTRAIL_IRQ_H_ - -#define PIRQA_APIC_IRQ 16 -#define PIRQB_APIC_IRQ 17 -#define PIRQC_APIC_IRQ 18 -#define PIRQD_APIC_IRQ 19 -#define PIRQE_APIC_IRQ 20 -#define PIRQF_APIC_IRQ 21 -#define PIRQG_APIC_IRQ 22 -#define PIRQH_APIC_IRQ 23 -/* The below IRQs are for when devices are in ACPI mode. Active low. */ -#define LPE_DMA0_IRQ 24 -#define LPE_DMA1_IRQ 25 -#define LPE_SSP0_IRQ 26 -#define LPE_SSP1_IRQ 27 -#define LPE_SSP2_IRQ 28 -#define LPE_IPC2HOST_IRQ 29 -#define LPSS_I2C1_IRQ 32 -#define LPSS_I2C2_IRQ 33 -#define LPSS_I2C3_IRQ 34 -#define LPSS_I2C4_IRQ 35 -#define LPSS_I2C5_IRQ 36 -#define LPSS_I2C6_IRQ 37 -#define LPSS_I2C7_IRQ 38 -#define LPSS_HSUART1_IRQ 39 -#define LPSS_HSUART2_IRQ 40 -#define LPSS_SPI_IRQ 41 -#define LPSS_DMA1_IRQ 42 -#define LPSS_DMA2_IRQ 43 -#define SCC_EMMC_IRQ 44 -#define SCC_SDIO_IRQ 46 -#define SCC_SD_IRQ 47 -#define GPIO_NC_IRQ 48 -#define GPIO_SC_IRQ 49 -#define GPIO_SUS_IRQ 50 -/* GPIO direct / dedicated IRQs. */ -#define GPIO_S0_DED_IRQ_0 51 -#define GPIO_S0_DED_IRQ_1 52 -#define GPIO_S0_DED_IRQ_2 53 -#define GPIO_S0_DED_IRQ_3 54 -#define GPIO_S0_DED_IRQ_4 55 -#define GPIO_S0_DED_IRQ_5 56 -#define GPIO_S0_DED_IRQ_6 57 -#define GPIO_S0_DED_IRQ_7 58 -#define GPIO_S0_DED_IRQ_8 59 -#define GPIO_S0_DED_IRQ_9 60 -#define GPIO_S0_DED_IRQ_10 61 -#define GPIO_S0_DED_IRQ_11 62 -#define GPIO_S0_DED_IRQ_12 63 -#define GPIO_S0_DED_IRQ_13 64 -#define GPIO_S0_DED_IRQ_14 65 -#define GPIO_S0_DED_IRQ_15 66 -#define GPIO_S5_DED_IRQ_0 67 -#define GPIO_S5_DED_IRQ_1 68 -#define GPIO_S5_DED_IRQ_2 69 -#define GPIO_S5_DED_IRQ_3 70 -#define GPIO_S5_DED_IRQ_4 71 -#define GPIO_S5_DED_IRQ_5 72 -#define GPIO_S5_DED_IRQ_6 73 -#define GPIO_S5_DED_IRQ_7 74 -#define GPIO_S5_DED_IRQ_8 75 -#define GPIO_S5_DED_IRQ_9 76 -#define GPIO_S5_DED_IRQ_10 77 -#define GPIO_S5_DED_IRQ_11 78 -#define GPIO_S5_DED_IRQ_12 79 -#define GPIO_S5_DED_IRQ_13 80 -#define GPIO_S5_DED_IRQ_14 81 -#define GPIO_S5_DED_IRQ_15 82 -/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL. */ -#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot -#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot -#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) -#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) - -/* PIC IRQ settings. */ -#define PIRQ_PIC_IRQ3 0x3 -#define PIRQ_PIC_IRQ4 0x4 -#define PIRQ_PIC_IRQ5 0x5 -#define PIRQ_PIC_IRQ6 0x6 -#define PIRQ_PIC_IRQ7 0x7 -#define PIRQ_PIC_IRQ9 0x9 -#define PIRQ_PIC_IRQ10 0xa -#define PIRQ_PIC_IRQ11 0xb -#define PIRQ_PIC_IRQ12 0xc -#define PIRQ_PIC_IRQ14 0xe -#define PIRQ_PIC_IRQ15 0xf -#define PIRQ_PIC_IRQDISABLE 0x80 -#define PIRQ_PIC_UNKNOWN_UNUSED 0xff - -/* Overloaded term, but these values determine the per device route. */ -#define PIRQA 0 -#define PIRQB 1 -#define PIRQC 2 -#define PIRQD 3 -#define PIRQE 4 -#define PIRQF 5 -#define PIRQG 6 -#define PIRQH 7 - -/* These registers live behind the ILB_BASE_ADDRESS */ -#define ACTL 0x00 -# define SCIS_MASK 0x07 -# define SCIS_IRQ9 0x00 -# define SCIS_IRQ10 0x01 -# define SCIS_IRQ11 0x02 -# define SCIS_IRQ20 0x04 -# define SCIS_IRQ21 0x05 -# define SCIS_IRQ22 0x06 -# define SCIS_IRQ23 0x07 - -/* In each mainboard directory there should exist a header file irqroute.h that - * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which - * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ - -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) -#include <stdint.h> - -#define NUM_OF_PCI_DEVS 32 -#define NUM_PIRQS 8 - -struct baytrail_irq_route { - /* Per device configuration. */ - uint16_t pcidev[NUM_OF_PCI_DEVS]; - /* Route path for each internal PIRQx in PIC mode. */ - uint8_t pic[NUM_PIRQS]; -}; - -extern const struct baytrail_irq_route global_baytrail_irq_route; - -#define DEFINE_IRQ_ROUTES \ - const struct baytrail_irq_route global_baytrail_irq_route = { \ - .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \ - .pic = { PIRQ_PIC_ROUTES, }, \ - } - -#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ - [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ - ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) - -#define PIRQ_PIC(pirq_, pic_irq_) \ - [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ - -/* used for ACPI only */ -#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - -#endif /* _BAYTRAIL_IRQ_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/lpc.h b/src/soc/intel/fsp_baytrail/include/soc/lpc.h deleted file mode 100644 index defd34a2f5..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/lpc.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_LPC_H_ -#define _BAYTRAIL_LPC_H_ - -/* PCI config registers in LPC bridge. */ -#define REVID 0x08 -#define ABASE 0x40 /* IO BAR */ -#define PBASE 0x44 /* MEM BAR */ -#define GBASE 0x48 /* IO BAR */ -#define IOBASE 0x4c /* MEM BAR */ -#define IBASE 0x50 /* MEM BAR */ -#define SBASE 0x54 /* MEM BAR */ -#define MPBASE 0x58 /* MEM BAR */ -#define PUBASE 0x5c -#define SET_BAR_ENABLE 0x02 -#define UART_CONT 0x80 -#define RCBA 0xf0 -#define RCBA_ENABLE 0x01 - -#define ILB_ACTL 0 -#define ILB_MC 0x4 -#define ILB_PIRQA_ROUT 0x8 -#define ILB_PIRQB_ROUT 0x9 -#define ILB_PIRQC_ROUT 0xA -#define ILB_PIRQD_ROUT 0xB -#define ILB_PIRQE_ROUT 0xC -#define ILB_PIRQF_ROUT 0xD -#define ILB_PIRQG_ROUT 0xE -#define ILB_PIRQH_ROUT 0xF -#define ILB_SERIRQ_CNTL 0x10 -#define SCNT_CONTINUOUS_MODE (1 << 7) -#define SCNT_QUIET_MODE 0 -#define ILB_IR00 0x20 -#define ILB_IR01 0x22 -#define ILB_IR02 0x24 -#define ILB_IR03 0x26 -#define ILB_IR04 0x28 -#define ILB_IR05 0x2A -#define ILB_IR06 0x2C -#define ILB_IR07 0x2E -#define ILB_IR08 0x30 -#define ILB_IR09 0x32 -#define ILB_IR10 0x34 -#define ILB_IR11 0x36 -#define ILB_IR12 0x38 -#define ILB_IR13 0x3A -#define ILB_IR14 0x3C -#define ILB_IR15 0x3E -#define ILB_IR16 0x40 -#define ILB_IR17 0x42 -#define ILB_IR18 0x44 -#define ILB_IR19 0x46 -#define ILB_IR20 0x48 -#define ILB_IR21 0x4A -#define ILB_IR22 0x4C -#define ILB_IR23 0x4E -#define ILB_IR24 0x50 -#define ILB_IR25 0x52 -#define ILB_IR26 0x54 -#define ILB_IR27 0x56 -#define ILB_IR28 0x58 -#define ILB_IR29 0x5A -#define ILB_IR30 0x5C -#define ILB_IR31 0x5E -#define ILB_OIC 0x60 -#define SIRQEN (1 << 12) -#define AEN (1 << 8) - -#define RID_A_STEPPING_START 1 -#define RID_B_STEPPING_START 5 -#define RID_C_STEPPING_START 0xe -#define RID_D_STEPPING_START 0x11 - -enum baytrail_stepping { - STEP_A0, - STEP_A1, - STEP_B0, - STEP_B1, - STEP_B2, - STEP_B3, - STEP_C0, - STEP_D0, -}; - -/* Registers behind the RCBA_BASE_ADDRESS bar. */ -#define GCS 0x00 -# define BILD (1 << 0) - -/* Default IO range claimed by the LPC devices. The upper bound is exclusive. */ -#define LPC_DEFAULT_IO_RANGE_LOWER 0 -#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 -#define IO_APIC_RANGE_SIZE 0x1000 - -#endif /* _BAYTRAIL_LPC_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h deleted file mode 100644 index 8edab59bdf..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_MSR_H_ -#define _BAYTRAIL_MSR_H_ - -#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd -#define MSR_PLATFORM_INFO 0xce -#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 -#define MSR_POWER_MISC 0x120 -#define MSR_POWER_CTL 0x1fc -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_LIMIT 0x610 -#define MSR_IACORE_RATIOS 0x66a -#define MSR_IACORE_TURBO_RATIOS 0x66c -#define MSR_IACORE_VIDS 0x66b -#define MSR_IACORE_TURBO_VIDS 0x66d - -/* Read BCLK from MSR */ -unsigned int bus_freq_khz(void); - -#endif /* _BAYTRAIL_MSR_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/nvs.h b/src/soc/intel/fsp_baytrail/include/soc/nvs.h deleted file mode 100644 index df2fc60d71..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/nvs.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_NVS_H_ -#define _BAYTRAIL_NVS_H_ - -#include <soc/device_nvs.h> - -typedef struct { - /* Miscellaneous */ - u16 osys; /* 0x00 - Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 prm0; /* 0x03 - SMI function call parameter */ - u8 prm1; /* 0x04 - SMI function call parameter */ - u8 scif; /* 0x05 - SCI function call (via _L00) */ - u8 prm2; /* 0x06 - SCI function call parameter */ - u8 prm3; /* 0x07 - SCI function call parameter */ - u8 lckf; /* 0x08 - Global Lock function for EC */ - u8 prm4; /* 0x09 - Lock function parameter */ - u8 prm5; /* 0x0a - Lock function parameter */ - u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ - u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ - u8 pcnt; /* 0x11 - Processor Count */ - u8 tpmp; /* 0x12 - TPM Present and Enabled */ - u8 tlvl; /* 0x13 - Throttle Level */ - u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ - u8 rsvd1[11]; - - /* Device Config */ - u8 s5u0; /* 0x20 - Enable USB0 in S5 */ - u8 s5u1; /* 0x21 - Enable USB1 in S5 */ - u8 s3u0; /* 0x22 - Enable USB0 in S3 */ - u8 s3u1; /* 0x23 - Enable USB1 in S3 */ - u8 tact; /* 0x24 - Thermal Active trip point */ - u8 tpsv; /* 0x25 - Thermal Passive trip point */ - u8 tcrt; /* 0x26 - Thermal Critical trip point */ - u8 dpte; /* 0x27 - Enable DPTF */ - u8 rsvd2[8]; - - /* Base Addresses */ - u32 obsolete_cmem; /* 0x30 - CBMEM TOC */ - u32 tolm; /* 0x34 - Top of Low Memory */ - u32 cbmc; /* 0x38 - coreboot memconsole */ - u8 rsvd3[196]; - - /* Pad 0x0100-0x0fff */ - u8 rsvd4[3840]; - - /* Baytrail LPSS (0x1000) */ - device_nvs_t dev; -} __packed global_nvs_t; - -void acpi_create_gnvs(global_nvs_t *gnvs); - -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); - -#endif /* _BAYTRAIL_NVS_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pattrs.h b/src/soc/intel/fsp_baytrail/include/soc/pattrs.h deleted file mode 100644 index 7b46345a47..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/pattrs.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _PATTRS_H_ -#define _PATTRS_H_ - -#include <stdint.h> -#include <cpu/x86/msr.h> - -enum { - IACORE_MIN, - IACORE_LFM, - IACORE_MAX, - IACORE_TURBO, - IACORE_END -}; - -/* The pattrs structure is a common place to stash pertinent information - * about the processor or platform. Instead of going to the source (msrs, cpuid) - * every time an attribute is needed use the pattrs structure. - */ -struct pattrs { - msr_t platform_id; - msr_t platform_info; - int iacore_ratios[IACORE_END]; - int iacore_vids[IACORE_END]; - uint32_t cpuid; - int revid; - int stepping; - const void *microcode_patch; - int address_bits; - int num_cpus; - unsigned int bclk_khz; -}; - -/* This is just to hide the abstraction w/o relying on how the underlying - * storage is allocated. */ -#define PATTRS_GLOB_NAME __global_pattrs -#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME -extern DEFINE_PATTRS; - -static inline const struct pattrs *pattrs_get(void) -{ - return &PATTRS_GLOB_NAME; -} - - -#endif /* _PATTRS_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h deleted file mode 100644 index 5e5b8071df..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_PCI_DEVS_H_ -#define _BAYTRAIL_PCI_DEVS_H_ - -#include <device/pci_def.h> - -#define BUS0 0 - -/* All these devices live on bus 0 with the associated device and function */ - -/* SoC transaction router */ -#define SOC_DEV 0x0 -#define SOC_FUNC 0 -# define SOC_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC) - - -/* Graphics and Display */ -#define GFX_DEV 0x2 -#define GFX_FUNC 0 -# define SOC_DEVFN_GFX PCI_DEVFN(GFX_DEV,GFX_FUNC) - -/* MIPI */ -#define MIPI_DEV 0x3 -#define MIPI_FUNC 0 -# define SOC_DEVFN_MIPI PCI_DEVFN(MIPI_DEV,MIPI_FUNC) - - -/* SDIO Port */ -#define EMMC_DEV 0x10 -#define EMMC_FUNC 0 -# define SOC_DEVFN_EMMC PCI_DEVFN(EMMC_DEV,EMMC_FUNC) - -/* SDIO Port */ -#define SDIO_DEV 0x11 -#define SDIO_FUNC 0 -# define SOC_DEVFN_SDIO PCI_DEVFN(SDIO_DEV,SDIO_FUNC) - -/* SD Port */ -#define SD_DEV 0x12 -#define SD_FUNC 0 -# define SOC_DEVFN_SD PCI_DEVFN(SD_DEV,SD_FUNC) - -/* SATA */ -#define SATA_DEV 0x13 -#define SATA_FUNC 0 -# define SOC_DEVFN_SATA PCI_DEVFN(SATA_DEV,SATA_FUNC) - -/* xHCI */ -#define XHCI_DEV 0x14 -#define XHCI_FUNC 0 -# define XHCI_FUS_REG 0xE0 -# define XHCI_FUNC_DISABLE (1 << 0) -# define XHCI_USB2PR_REG 0xD0 -# define SOC_DEVFN_XHCI PCI_DEVFN(XHCI_DEV,XHCI_FUNC) - -/* LPE Audio */ -#define LPE_DEV 0x15 -#define LPE_FUNC 0 -# define SOC_DEVFN_LPE PCI_DEVFN(LPE_DEV,LPE_FUNC) - -/* OTG */ -#define OTG_DEV 0x16 -#define OTG_FUNC 0 -# define SOC_DEVFN_OTG PCI_DEVFN(LPE_DEV,LPE_FUNC) - -/* MMC Port */ -#define MMC45_DEV 0x17 -#define MMC45_FUNC 0 -# define SOC_DEVFN_MMC45 PCI_DEVFN(MMC45_DEV,MMC45_FUNC) - -/* Serial IO 1 */ -#define SIO1_DEV 0x18 -# define SIO_DMA1_DEV SIO1_DEV -# define SIO_DMA1_FUNC 0 -# define I2C1_DEV SIO1_DEV -# define I2C1_FUNC 1 -# define I2C2_DEV SIO1_DEV -# define I2C2_FUNC 2 -# define I2C3_DEV SIO1_DEV -# define I2C3_FUNC 3 -# define I2C4_DEV SIO1_DEV -# define I2C4_FUNC 4 -# define I2C5_DEV SIO1_DEV -# define I2C5_FUNC 5 -# define I2C6_DEV SIO1_DEV -# define I2C6_FUNC 6 -# define I2C7_DEV SIO1_DEV -# define I2C7_FUNC 7 -# define SOC_DEVFN_SIO_DMA1 PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) -# define SOC_DEVFN_I2C1 PCI_DEVFN(I2C1_DEV,I2C1_FUNC) -# define SOC_DEVFN_I2C2 PCI_DEVFN(I2C2_DEV,I2C2_FUNC) -# define SOC_DEVFN_I2C3 PCI_DEVFN(I2C3_DEV,I2C3_FUNC) -# define SOC_DEVFN_I2C4 PCI_DEVFN(I2C4_DEV,I2C4_FUNC) -# define SOC_DEVFN_I2C5 PCI_DEVFN(I2C5_DEV,I2C5_FUNC) -# define SOC_DEVFN_I2C6 PCI_DEVFN(I2C6_DEV,I2C6_FUNC) -# define SOC_DEVFN_I2C7 PCI_DEVFN(I2C7_DEV,I2C7_FUNC) - -#define PCH_DEV_SLOT_I2C1 I2C1_DEV - -/* Trusted Execution Engine */ -#define TXE_DEV 0x1a -#define TXE_FUNC 0 -# define SOC_DEVFN_TXE PCI_DEVFN(TXE_DEV,TXE_FUNC) - -/* HD Audio */ -#define HDA_DEV 0x1b -#define HDA_FUNC 0 -# define SOC_DEVFN_HDA PCI_DEVFN(HDA_DEV,HDA_FUNC) - -/* PCIe Ports */ -#define PCIE_DEV 0x1c -# define PCIE_PORT1_DEV PCIE_DEV -# define PCIE_PORT1_FUNC 0 -# define PCIE_PORT2_DEV PCIE_DEV -# define PCIE_PORT2_FUNC 1 -# define PCIE_PORT3_DEV PCIE_DEV -# define PCIE_PORT3_FUNC 2 -# define PCIE_PORT4_DEV PCIE_DEV -# define PCIE_PORT4_FUNC 3 -# define SOC_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) -# define SOC_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) -# define SOC_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) -# define SOC_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC) - -/* EHCI */ -#define EHCI_DEV 0x1d -#define EHCI_FUNC 0 -# define SOC_DEVFN_EHCI PCI_DEVFN(EHCI_DEV,EHCI_FUNC) - -/* Serial IO 2 */ -#define SIO2_DEV 0x1e -# define SIO_DMA2_DEV SIO2_DEV -# define SIO_DMA2_FUNC 0 -# define PWM1_DEV SIO2_DEV -# define PWM1_FUNC 1 -# define PWM2_DEV SIO2_DEV -# define PWM2_FUNC 2 -# define HSUART1_DEV SIO2_DEV -# define HSUART1_FUNC 3 -# define HSUART2_DEV SIO2_DEV -# define HSUART2_FUNC 4 -# define SPI_DEV SIO2_DEV -# define SPI_FUNC 5 -# define SOC_DEVFN_SIO_DMA2 PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) -# define SOC_DEVFN_PWM1 PCI_DEVFN(PWM1_DEV,PWM1_FUNC) -# define SOC_DEVFN_PWM2 PCI_DEVFN(PWM2_DEV,PWM2_FUNC) -# define SOC_DEVFN_HSUART1 PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) -# define SOC_DEVFN_HSUART2 PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) -# define SOC_DEVFN_SPI PCI_DEVFN(SPI_DEV,SPI_FUNC) - - -/* Platform Controller Unit */ -#define PCU_DEV 0x1f -# define LPC_DEV PCU_DEV -# define LPC_FUNC 0 -# define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) -# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) - -# define SMBUS_DEV PCU_DEV -# define SMBUS_FUNC 3 -# define SOC_DEVFN_SMBUS PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) - -#define SOC_DEVID 0x0f00 -#define GFX_DEVID 0x0f31 -#define MIPI_DEVID 0x0f38 -#define EMMC_DEVID 0x0f14 -#define SDIO_DEVID 0x0f15 -#define SD_DEVID 0x0f16 -#define IDE1_DEVID 0x0f20 -#define IDE2_DEVID 0x0f21 -#define AHCI1_DEVID 0x0f22 -#define AHCI2_DEVID 0x0f23 -#define XHCI_DEVID 0x0f35 -#define LPE_DEVID 0x0f28 -#define OTG_DEVID 0x0f37 -#define MMC45_DEVID 0x0f50 -#define SIO_DMA1_DEVID 0x0f40 -#define I2C1_DEVID 0x0f41 -#define I2C2_DEVID 0x0f42 -#define I2C3_DEVID 0x0f43 -#define I2C4_DEVID 0x0f44 -#define I2C5_DEVID 0x0f45 -#define I2C6_DEVID 0x0f46 -#define I2C7_DEVID 0x0f47 -#define TXE_DEVID 0x0f18 -#define HDA_DEVID 0x0f04 -#define PCIE_PORT1_DEVID 0x0f48 -#define PCIE_PORT2_DEVID 0x0f4a -#define PCIE_PORT3_DEVID 0x0f4c -#define PCIE_PORT4_DEVID 0x0f4e -#define EHCI_DEVID 0x0f34 -#define SIO_DMA2_DEVID 0x0f06 -#define PWM1_DEVID 0x0f08 -#define PWM2_DEVID 0x0f09 -#define HSUART1_DEVID 0x0f0a -#define HSUART2_DEVID 0x0f0c -#define SPI_DEVID 0xf0e -#define LPC_DEVID 0x0f1c -#define SMBUS_DEVID 0x0f12 - -#endif /* _BAYTRAIL_PCI_DEVS_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pcie.h b/src/soc/intel/fsp_baytrail/include/soc/pcie.h deleted file mode 100644 index 9d2d3de53e..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/pcie.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_PCIE_H_ -#define _BAYTRAIL_PCIE_H_ - -/* PCIe root port config space registers. */ -#define XCAP 0x40 -# define SI (1 << 24) -#define DCAP 0x44 -# define MPS_MASK 0x7 -#define DCTL_DSTS 0x48 -# define URE (1 << 3) -# define FEE (1 << 2) -# define NFE (1 << 1) -# define CEE (1 << 0) -#define LCAP 0x4c -# define L1EXIT_SHIFT 15 -# define L1EXIT_MASK (0x7 << L1EXIT_SHIFT) -#define LCTL 0x50 -# define CCC (1 << 6) -# define RL (1 << 5) -# define LD (1 << 4) -#define LSTS 0x52 -#define SLCAP 0x54 -# define SLN_SHIFT 19 -# define SLS_SHIFT 15 -# define SLV_SHIFT 7 -# define HPC (1 << 6) -# define HPS (1 << 5) -#define SLCTL_SLSTS 0x58 -# define PDS (1 << 22) -#define DCAP2 0x64 -# define OBFFS (0x3 << 18) -# define LTRMS (1 << 11) -#define DSTS2 0x68 -# define OBFFEN (3 << 13) -# define LTRME (1 << 10) -# define CTD (1 << 4) -#define CHCFG 0xd0 -# define UPSD (1 << 24) -# define UNRS (1 << 15) -# define UPRS (1 << 14) -#define MPC2 0xd4 -# define IPF (1 << 11) -# define LSTP (1 << 6) -# define EOIFD (1 << 1) -#define MPC 0xd8 -# define CCEL_SHIFT 15 -# define CCEL_MASK (0x7 << CCEL_SHIFT) -#define RPPGEN 0xe0 -# define RPSCGEN (1 << 15) -# define LCLKREQEN (1 << 13) -# define BBCLKREQEN (1 << 12) -# define SRDLCGEN (1 << 11) -# define SRDBCGEN (1 << 10) -# define RPDLCGEN (1 << 9) -# define RPDBCGEN (1 << 8) -#define PWRCTL 0xe8 -# define RPL1SQPOL (1 << 1) -# define RPDTSQPOL (1 << 0) -#define PHYCTL2_IOSFBCTL 0xf4 -# define PLL_OFF_EN (1 << 8) -# define TDFT (3 << 14) -# define TXCFGCHWAIT (3 << 12) -# define SIID (3 << 26) -#define STRPFUSECFG 0xfc -# define LANECFG_SHIFT 14 -# define LANECFG_MASK (0x3 << LANECFG_SHIFT) -#define AERCH 0x100 -#define NFTS 0x314 -#define L0SC 0x318 -#define CFG2 0x320 -# define CSREN (1 << 22) -# define LATGC_SHIFT 6 -# define LATGC_MASK (0x7 << LATGC_SHIFT) -#define PCIEDBG 0x324 -# define SPCE (1 << 5) -#define PCIESTS1 0x328 -#define PCIEALC 0x338 -#define RTP 0x33c -#define PHYCTL4 0x408 -# define SQDIS (1 << 27) - - -#endif /* _BAYTRAIL_PCIE_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h deleted file mode 100644 index 9e588addae..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ /dev/null @@ -1,292 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_PMC_H_ -#define _BAYTRAIL_PMC_H_ - -#include <arch/acpi.h> - -#define IOCOM1 0x3f8 - -/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ -#define PRSTS 0x00 -# define PMC_WDT_STS (1 << 15) -# define SEC_GBLRST_STS (1 << 7) -# define SEC_WDT_STS (1 << 6) -# define WOL_OVR_WK_STS (1 << 5) -# define PMC_WAKE_STS (1 << 4) -#define PMC_CFG 0x08 -# define SPS (1 << 5) -# define NO_REBOOT (1 << 4) -# define SX_ENT_TO_EN (1 << 3) -# define TIMING_T581_SHIFT (0) -# define TIMING_T581_MASK (3 << TIMING_T581_SHIFT) -# define TIMING_T581_10uS (0 << TIMING_T581_SHIFT) -# define TIMING_T581_100uS (1 << TIMING_T581_SHIFT) -# define TIMING_T581_1mS (2 << TIMING_T581_SHIFT) -# define TIMING_T581_10mS (3 << TIMING_T581_SHIFT) -#define VLV_PM_STS 0x0c -# define PMC_MSG_FULL_STS (1 << 24) -# define PMC_MSG_4_FULL_STS (1 << 23) -# define PMC_MSG_3_FULL_STS (1 << 22) -# define PMC_MSG_2_FULL_STS (1 << 21) -# define PMC_MSG_1_FULL_STS (1 << 20) -# define CODE_REQ (1 << 8) -# define HPR_ENT_TO (1 << 2) -# define SX_ENT_TO (1 << 1) -#define GEN_PMCON1 0x20 -# define UART_EN (1 << 24) -# define DISB (1 << 23) -# define MEM_SR (1 << 21) -# define SRS (1 << 20) -# define CTS (1 << 19) -# define MS4V (1 << 18) -# define PWR_FLR (1 << 16) -# define PME_B0_S5_DIS (1 << 15) -# define SUS_PWR_FLR (1 << 14) -# define WOL_EN_OVRD (1 << 13) -# define DIS_SLP_X_STRCH_SUS_UP (1 << 12) -# define GEN_RST_STS (1 << 9) -# define RPS (1 << 2) -# define AFTERG3_EN (1 << 0) -#define GEN_PMCON2 0x24 -# define SLPSX_STR_POL_LOCK (1 << 18) -# define BIOS_PCI_EXP_EN (1 << 10) -# define PWRBTN_LVL (1 << 9) -# define SMI_LOCK (1 << 4) -#define ETR 0x48 -# define CF9LOCK (1 << 31) -# define LTR_DEF (1 << 22) -# define IGNORE_HPET (1 << 21) -# define CF9GR (1 << 20) -# define CWORWRE (1 << 18) -#define FUNC_DIS 0x34 -# define SIO_DMA2_DIS (1 << 0) -# define PWM1_DIS (1 << 1) -# define PWM2_DIS (1 << 2) -# define HSUART1_DIS (1 << 3) -# define HSUART2_DIS (1 << 4) -# define SPI_DIS (1 << 5) -# define SDIO_DIS (1 << 9) -# define SD_DIS (1 << 10) -# define MMC_DIS (1 << 11) -# define HDA_DIS (1 << 12) -# define LPE_DIS (1 << 13) -# define OTG_DIS (1 << 14) -# define XHCI_DIS (1 << 15) -# define SATA_DIS (1 << 17) -# define EHCI_DIS (1 << 18) -# define TXE_DIS (1 << 19) -# define PCIE_PORT1_DIS (1 << 20) -# define PCIE_PORT2_DIS (1 << 21) -# define PCIE_PORT3_DIS (1 << 22) -# define PCIE_PORT4_DIS (1 << 23) -# define SIO_DMA1_DIS (1 << 24) -# define I2C1_DIS (1 << 25) -# define I2C2_DIS (1 << 26) -# define I2C3_DIS (1 << 27) -# define I2C4_DIS (1 << 28) -# define I2C5_DIS (1 << 29) -# define I2C6_DIS (1 << 30) -# define I2C7_DIS (1 << 31) -#define FUNC_DIS2 0x38 -# define USH_SS_PHY_DIS (1 << 2) -# define OTG_SS_PHY_DIS (1 << 1) -# define SMBUS_DIS (1 << 0) -#define GPIO_ROUT 0x58 -# define ROUTE_MASK 3 -# define ROUTE_NONE 0 -# define ROUTE_SMI 1 -# define ROUTE_SCI 2 -#define PLT_CLK_CTL_0 0x60 -#define PLT_CLK_CTL_1 0x64 -#define PLT_CLK_CTL_2 0x68 -#define PLT_CLK_CTL_3 0x6c -#define PLT_CLK_CTL_4 0x70 -#define PLT_CLK_CTL_5 0x74 -# define CLK_FREQ_25MHZ (0x0 << 2) -# define CLK_FREQ_19P2MHZ (0x1 << 2) -# define CLK_CTL_D3_LPE (0x0 << 0) -# define CLK_CTL_ON (0x1 << 0) -# define CLK_CTL_OFF (0x2 << 0) -#define PME_STS 0xc0 -#define GPE_LEVEL_EDGE 0xc4 -# define GPE_EDGE 0 -# define GPE_LEVEL 1 -#define GPE_POLARITY 0xc8 -# define GPE_ACTIVE_HIGH 1 -# define GPE_ACTIVE_LOW 0 -#define LOCK 0xcc - -/* IO Mapped registers behind ACPI_BASE_ADDRESS */ -#define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define USB_STS (1 << 13) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define TMROF_STS (1 << 0) -#define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define USB_WAKE_EN (1 << 13) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) -#define PM1_CNT 0x04 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) -#define PM1_TMR 0x08 -#define GPE0_STS 0x20 -#define CORE_GPIO_STS7 (1 << 31) -#define CORE_GPIO_STS6 (1 << 30) -#define CORE_GPIO_STS5 (1 << 29) -#define CORE_GPIO_STS4 (1 << 28) -#define CORE_GPIO_STS3 (1 << 27) -#define CORE_GPIO_STS2 (1 << 26) -#define CORE_GPIO_STS1 (1 << 25) -#define CORE_GPIO_STS0 (1 << 24) -#define SUS_GPIO_STS7 (1 << 23) -#define SUS_GPIO_STS6 (1 << 22) -#define SUS_GPIO_STS5 (1 << 21) -#define SUS_GPIO_STS4 (1 << 20) -#define SUS_GPIO_STS3 (1 << 19) -#define SUS_GPIO_STS2 (1 << 18) -#define SUS_GPIO_STS1 (1 << 17) -#define SUS_GPIO_STS0 (1 << 16) -#define PME_B0_STS_BIT 13 -#define PME_B0_STS (1 << PME_B0_STS_BIT) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define PCIE_WAKE3_STS (1 << 8) -#define PCIE_WAKE2_STS (1 << 7) -#define PCIE_WAKE1_STS (1 << 6) -#define GUNIT_SCI_STS (1 << 5) -#define PUNIT_SCI_STS (1 << 4) -#define PCIE_WAKE0_STS (1 << 3) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) -#define GPE0_EN 0x28 -#define CORE_GPIO_EN7 (1 << 31) -#define CORE_GPIO_EN6 (1 << 30) -#define CORE_GPIO_EN5 (1 << 29) -#define CORE_GPIO_EN4 (1 << 28) -#define CORE_GPIO_EN3 (1 << 27) -#define CORE_GPIO_EN2 (1 << 26) -#define CORE_GPIO_EN1 (1 << 25) -#define CORE_GPIO_EN0 (1 << 24) -#define SUS_GPIO_EN7_BIT 23 -#define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT) -#define SUS_GPIO_EN6_BIT 22 -#define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT) -#define SUS_GPIO_EN5_BIT 21 -#define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT) -#define SUS_GPIO_EN4_BIT 20 -#define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT) -#define SUS_GPIO_EN3_BIT 19 -#define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT) -#define SUS_GPIO_EN2_BIT 18 -#define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT) -#define SUS_GPIO_EN1_BIT 17 -#define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT) -#define SUS_GPIO_EN0_BIT 16 -#define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT) -#define PME_B0_EN (1 << 13) -#define BATLOW_EN (1 << 10) -#define PCI_EXP_EN (1 << 9) -#define PCIE_WAKE3_EN (1 << 8) -#define PCIE_WAKE2_EN (1 << 7) -#define PCIE_WAKE1_EN (1 << 6) -#define PCIE_WAKE0_EN (1 << 3) -#define SWGPE_EN (1 << 2) -#define HOT_PLUG_EN (1 << 1) -#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT -#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x) -#define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define USB_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? -#define SMI_STS 0x34 -#define ALT_GPIO_SMI 0x38 -#define UPRWC 0x3c -# define UPRWC_WR_EN (1 << 1) // USB Per-Port Registers Write Enable -#define GPE_CTRL 0x40 -#define PM2A_CNT_BLK 0x50 -#define TCO_RLD 0x60 -#define TCO_STS 0x64 -# define SECOND_TO_STS (1 << 17) -# define TCO_TIMEOUT (1 << 3) -#define TCO1_CNT 0x68 -# define TCO_LOCK (1 << 12) -# define TCO_TMR_HALT (1 << 11) -#define TCO_TMR 0x70 - -/* I/O ports */ -#define RST_CNT 0xcf9 -# define FULL_RST (1 << 3) -# define RST_CPU (1 << 2) -# define SYS_RST (1 << 1) - -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) - -/* Track power state from reset to log events. */ -struct chipset_power_state { - uint16_t pm1_sts; - uint16_t pm1_en; - uint32_t pm1_cnt; - uint32_t gpe0_sts; - uint32_t gpe0_en; - uint32_t tco_sts; - uint32_t prsts; - uint32_t gen_pmcon1; - uint32_t gen_pmcon2; -} __packed; - -/* Power Management Utility Functions. */ -uint16_t get_pmbase(void); -uint32_t clear_smi_status(void); -uint16_t clear_pm1_status(void); -uint32_t clear_tco_status(void); -uint32_t clear_gpe_status(void); -uint32_t clear_alt_status(void); -void clear_pmc_status(void); -void enable_smi(uint32_t mask); -void disable_smi(uint32_t mask); -void enable_pm1(uint16_t events); -void enable_pm1_control(uint32_t mask); -void disable_pm1_control(uint32_t mask); -void enable_gpe(uint32_t mask); -void disable_gpe(uint32_t mask); -void disable_all_gpe(void); - -uint32_t chipset_prev_sleep_state(uint32_t clear); - -void southcluster_log_state(void); - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - -#endif /* _BAYTRAIL_PMC_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h deleted file mode 100644 index 45fda9e937..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_RAMSTAGE_H_ -#define _BAYTRAIL_RAMSTAGE_H_ - -#include <device/device.h> - -/* The baytrail_init_pre_device() function is called prior to device - * initialization, but it's after console and cbmem has been reinitialized. */ -void baytrail_init_pre_device(void); -void baytrail_init_cpus(struct device *dev); -void southcluster_enable_dev(struct device *dev); -void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); - -extern struct pci_operations soc_pci_ops; - -#endif /* _BAYTRAIL_RAMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h deleted file mode 100644 index dce953993a..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_ROMSTAGE_H_ -#define _BAYTRAIL_ROMSTAGE_H_ - -#include <stdint.h> -#include <drivers/intel/fsp1_0/fsp_util.h> - -void main(FSP_INFO_HEADER *fsp_info_header); - -#define NUM_ROMSTAGE_TS 4 - -void tco_disable(void); -void punit_init(void); -void early_mainboard_romstage_entry(void); -void late_mainboard_romstage_entry(void); -void get_func_disables(uint32_t *mask, uint32_t *mask2); -void byt_config_com1_and_enable(void); - -#endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/smm.h b/src/soc/intel/fsp_baytrail/include/soc/smm.h deleted file mode 100644 index b6e24a8a0f..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/smm.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_SMM_H_ -#define _BAYTRAIL_SMM_H_ - - -#endif /* _BAYTRAIL_SMM_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/spi.h b/src/soc/intel/fsp_baytrail/include/soc/spi.h deleted file mode 100644 index 1ac0b59e56..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/spi.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_SPI_H_ -#define _BAYTRAIL_SPI_H_ - -#include <stdint.h> - -/* These registers live behind SPI_BASE_ADDRESS. */ -#define HSFSTS 0x04 -# define FLOCKDN (0x1 << 15) -#define PREOP 0x94 -#define OPTYPE 0x96 -#define OPMENU0 0x98 -#define OPMENU1 0x9c -#define LVSCC 0xc4 -# define VCL (0x1 << 23) -# define EO(x) (((x) & 0xff) << 8) -# define WG_1_BYTE (0x0 << 2) -# define WG_64_BYTE (0x1 << 2) -# define BES_256_BYTE (0x0 << 0) -# define BES_4_KB (0x1 << 0) -# define BES_8_KB (0x2 << 0) -# define BES_64_KB (0x3 << 0) -#define UVSCC 0xc8 -#define SCS 0xf8 -# define SMIWPEN (0x1 << 7) -#define BCR 0xfc -# define EISS (0x1 << 5) -# define SRC_MASK (0x3 << 2) -# define SRC_CACHE_NO_PREFETCH (0x0 << 2) -# define SRC_NO_CACHE_NO_PREFETCH (0x1 << 2) -# define SRC_CACHE_PREFETCH (0x2 << 2) -# define BCR_LE (0x1 << 1) -# define BCR_WPD (0x1 << 0) - -/* - * SPI lockdown configuration. - */ -struct spi_config { - uint16_t preop; - uint16_t optype; - uint32_t opmenu[2]; - uint32_t lvscc; - uint32_t uvscc; -}; - -/* Return 0 on success < 0 on failure. */ -int mainboard_get_spi_config(struct spi_config *cfg); - -#endif /* _BAYTRAIL_SPI_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/xhci.h b/src/soc/intel/fsp_baytrail/include/soc/xhci.h deleted file mode 100644 index d509b51a6a..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/xhci.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef BAYTRAIL_XHCI_H -#define BAYTRAIL_XHCI_H - -/* XHCI PCI Registers */ -#define XHCI_PWR_CTL_STS 0x74 -#define XHCI_USB2PR 0xd0 -#define XHCI_USB2PRM 0xd4 -#define XHCI_USB3PR 0xd8 -#define XHCI_USB3PRM 0xdc -#define XHCI_USB2PDO 0xe4 -#define XHCI_USB3PDO 0xe8 - -/* XHCI Memory Registers */ -#define XHCI_USB3_PORTSC(port) (0x4e0 + (port * 0x10)) -# define XHCI_USB3_PORTSC_CHST (0x7f << 17) -# define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ -# define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */ -# define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ -# define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ -# define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ -# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ -# define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ -# define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ -# define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ -# define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ -# define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ -# define XHCI_PLSW_ENABLE (5 << 5) /* Enable port */ - -/* The Fuse register is incorrect for Baytrail-M so use hardcoded values */ -#define BYTM_USB2_PORT_COUNT 4 -#define BYTM_USB2_PORT_MAP 0xf -#define BYTM_USB3_PORT_COUNT 1 -#define BYTM_USB3_PORT_MAP 0x1 - -#define XHCI_RESET_TIMEOUT 100000 /* 100ms */ - -#endif /* BAYTRAIL_XHCI_H */ |