diff options
| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-06-08 21:41:42 -0700 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-11 05:52:03 +0000 |
| commit | a96be277e1062796be7109a08a9ab9cdb6bf5d28 (patch) | |
| tree | 82f7e6433049613a67f6c831ae4044b5947b92e1 /src/soc/intel/elkhartlake/chip.h | |
| parent | 08938a9be3fd5f02650926f87d00d0029fafc3c2 (diff) | |
soc/intel/elkhartlake: Update FSP-S PM & Thermal related configs
Further add initial Silicon UPD settings for thermal and power
management stuffs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I04ded059c36f18925b7a74c934fef2566c3db8fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/elkhartlake/chip.h')
| -rw-r--r-- | src/soc/intel/elkhartlake/chip.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index f51e723c8d..3df1ece8e0 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -63,6 +63,10 @@ struct soc_intel_elkhartlake_config { /* TCC activation offset */ uint32_t tcc_offset; + uint32_t tcc_offset_clamp; + + /* Memory Thermal Throttling: Enable - Default (0) / Disable (1) */ + bool MemoryThermalThrottlingDisable; /* System Agent dynamic frequency support. * When enabled memory will be trained at different frequencies. @@ -366,6 +370,12 @@ struct soc_intel_elkhartlake_config { * - PM_CFG.SLP_LAN_MIN_ASST_WDTH */ uint8_t PchPmPwrCycDur; + + /* + * PCH power button override period. + * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s + */ + u8 PchPmPwrBtnOverridePeriod; }; typedef struct soc_intel_elkhartlake_config config_t; |