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authorLean Sheng Tan <lean.sheng.tan@intel.com>2021-06-08 21:41:42 -0700
committerWerner Zeh <werner.zeh@siemens.com>2021-06-11 05:52:03 +0000
commita96be277e1062796be7109a08a9ab9cdb6bf5d28 (patch)
tree82f7e6433049613a67f6c831ae4044b5947b92e1 /src
parent08938a9be3fd5f02650926f87d00d0029fafc3c2 (diff)
soc/intel/elkhartlake: Update FSP-S PM & Thermal related configs
Further add initial Silicon UPD settings for thermal and power management stuffs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I04ded059c36f18925b7a74c934fef2566c3db8fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/55335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/elkhartlake/chip.h10
-rw-r--r--src/soc/intel/elkhartlake/fsp_params.c83
2 files changed, 93 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index f51e723c8d..3df1ece8e0 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -63,6 +63,10 @@ struct soc_intel_elkhartlake_config {
/* TCC activation offset */
uint32_t tcc_offset;
+ uint32_t tcc_offset_clamp;
+
+ /* Memory Thermal Throttling: Enable - Default (0) / Disable (1) */
+ bool MemoryThermalThrottlingDisable;
/* System Agent dynamic frequency support.
* When enabled memory will be trained at different frequencies.
@@ -366,6 +370,12 @@ struct soc_intel_elkhartlake_config {
* - PM_CFG.SLP_LAN_MIN_ASST_WDTH
*/
uint8_t PchPmPwrCycDur;
+
+ /*
+ * PCH power button override period.
+ * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s
+ */
+ u8 PchPmPwrBtnOverridePeriod;
};
typedef struct soc_intel_elkhartlake_config config_t;
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index 611d12b493..213fc8c7f1 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -22,6 +22,24 @@
/* Native function controls pads termination */
#define GPIO_TERM_NATIVE 0x1F
+/* PM related values */
+/* Imon offset is defined in 1/1000 increments */
+#define IMON_OFFSET 1
+/* Policy Imon slope is defined in 1/100 increments */
+#define IMON_SLOPE 100
+/* Thermal Design Current current limit in 1/8A units */
+#define TDC_CURRENT_LIMIT_MAX 112
+/* AcLoadline in 1/100 mOhms */
+#define AC_LOADLINE_LANE_0_MAX 112
+#define AC_LOADLINE_LANE_1_MAX 3
+/* DcLoadline in 1/100 mOhms */
+#define DC_LOADLINE_LANE_0_MAX 92
+#define DC_LOADLINE_LANE_1_MAX 3
+/* VR Icc Max limit. 0-255A in 1/4 A units */
+#define ICC_LIMIT_MAX 104
+/* Core Ratio Limit: For overclocking part: LFM to Fused */
+#define CORE_RATIO_LIMIT 0x13
+
/*
* Chip config parameter PcieRpL1Substates uses (UPD value + 1)
* because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
@@ -261,6 +279,71 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->ScsEmmcDdr50Enabled = config->ScsEmmcDdr50Enabled;
}
+ /* Thermal config */
+ dev = pcidev_path_on_root(SA_DEVFN_DPTF);
+ params->Device4Enable = is_dev_enabled(dev);
+ params->ProcHotResponse = 0x0; //Disable PROCHOT response
+ /* Thermal sensor (TS) target width */
+ params->DmiTS0TW = 3;
+ params->DmiTS1TW = 2;
+ params->DmiTS2TW = 1;
+ /* Enable memory thermal throttling by default */
+ if (!config->MemoryThermalThrottlingDisable) {
+ params->PchMemoryPmsyncEnable[0] = 1;
+ params->PchMemoryPmsyncEnable[1] = 1;
+ params->PchMemoryC0TransmitEnable[0] = 1;
+ params->PchMemoryC0TransmitEnable[1] = 1;
+ }
+
+ /* TccActivationOffset config */
+ params->TccActivationOffset = config->tcc_offset;
+ params->TccOffsetClamp = config->tcc_offset_clamp;
+ params->TccOffsetLock = 0x1; //lock Tcc Offset register
+
+ /* Power management config */
+ params->ImonSlope[0] = IMON_SLOPE;
+ params->ImonOffset[0] = IMON_OFFSET;
+ params->TdcCurrentLimit[0] = TDC_CURRENT_LIMIT_MAX;
+ params->AcLoadline[0] = AC_LOADLINE_LANE_0_MAX;
+ params->DcLoadline[0] = DC_LOADLINE_LANE_0_MAX;
+ params->AcLoadline[1] = AC_LOADLINE_LANE_1_MAX;
+ params->DcLoadline[1] = DC_LOADLINE_LANE_1_MAX;
+ params->IccMax[0] = ICC_LIMIT_MAX;
+ params->OneCoreRatioLimit = CORE_RATIO_LIMIT;
+ params->TwoCoreRatioLimit = CORE_RATIO_LIMIT;
+ params->ThreeCoreRatioLimit = CORE_RATIO_LIMIT;
+ params->FourCoreRatioLimit = CORE_RATIO_LIMIT;
+ params->FiveCoreRatioLimit = CORE_RATIO_LIMIT;
+ params->SixCoreRatioLimit = CORE_RATIO_LIMIT;
+ params->SevenCoreRatioLimit = CORE_RATIO_LIMIT;
+ params->EightCoreRatioLimit = CORE_RATIO_LIMIT;
+ params->PsysPmax = 0; //Set max platform power to auto profile
+ params->Custom1TurboActivationRatio = 0;
+ params->Custom2TurboActivationRatio = 0;
+ params->Custom3TurboActivationRatio = 0;
+ params->PchPwrOptEnable = 0x1; //Enable PCH DMI Power Optimizer
+ params->TStates = 0x0; //Disable T state
+ params->PkgCStateLimit = 0x7; //Set C state limit to C9
+ params->FastPkgCRampDisable[0] = 0x1;
+ params->SlowSlewRate[0] = 0x1;
+ params->MaxRatio = 0x8; //Set max P state ratio
+ params->PchEspiLgmrEnable = 0;
+ params->PchPmPwrBtnOverridePeriod = config->PchPmPwrBtnOverridePeriod;
+ params->PchS0ixAutoDemotion = 0;
+ params->PmcV1p05PhyExtFetControlEn = 0x1;
+ params->PmcV1p05IsExtFetControlEn = 0x1;
+ /* FIVR config */
+ params->PchFivrExtV1p05RailEnabledStates = 0x1E;
+ params->PchFivrExtV1p05RailSupportedVoltageStates = 0x2;
+ params->PchFivrExtVnnRailEnabledStates = 0x1E;
+ params->PchFivrExtVnnRailSupportedVoltageStates = 0xE;
+ params->PchFivrExtVnnRailSxEnabledStates = 0x1C;
+ params->PchFivrVccinAuxLowToHighCurModeVolTranTime = 0x0C;
+ params->PchFivrVccinAuxRetToHighCurModeVolTranTime = 0x36;
+ params->PchFivrVccinAuxRetToLowCurModeVolTranTime = 0x2B;
+ params->PchFivrVccinAuxOffToHighCurModeVolTranTime = 0x0096;
+ params->FivrSpreadSpectrum = 0xF;
+
/* Override/Fill FSP Silicon Param for mainboard */
mainboard_silicon_init_params(params);
}