diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2016-07-24 00:36:12 +0530 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@intel.com> | 2016-07-28 05:15:58 +0200 |
| commit | e4a8537ce20d801a5985ba6268ae83593063a4bf (patch) | |
| tree | efdc7dcf51a9b91f8d4f6f8db9c8a0ef951ca62d /src/soc/intel/common | |
| parent | 68d5d8b28ab399b8dfb8ef6477d25311a319f2d5 (diff) | |
soc/intel/skylake: Add C entry bootblock support
List of activity performing in this patch
- early PCH programming
- early SA programming
- early CPU programming
- mainborad early gpio programming for UART and SPI
- car setup
- move chipset programming from verstage to post console
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x34
Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index e9ad5082b4..429c61c2e1 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -3,6 +3,9 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) verstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +bootblock-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +bootblock-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c + romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c |