From e4a8537ce20d801a5985ba6268ae83593063a4bf Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sun, 24 Jul 2016 00:36:12 +0530 Subject: soc/intel/skylake: Add C entry bootblock support List of activity performing in this patch - early PCH programming - early SA programming - early CPU programming - mainborad early gpio programming for UART and SPI - car setup - move chipset programming from verstage to post console BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and booted kunimitsu till POST code 0x34 Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143 Signed-off-by: Barnali Sarkar Signed-off-by: Naveen Krishna Chatradhi Signed-off-by: Rizwan Qureshi Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/15785 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/common/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/common') diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index e9ad5082b4..429c61c2e1 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -3,6 +3,9 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) verstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +bootblock-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +bootblock-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c + romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c -- cgit v1.2.3