diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2021-09-01 23:32:23 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-16 13:09:58 +0000 |
| commit | d107e810c9b188bd313c25638a2878bd4fc61615 (patch) | |
| tree | 0bc1da2c77b1d0da1ce0ca6403348634a69f4e35 /src/soc/intel/common/pch/lockdown | |
| parent | 169302aa7f52c9d9e842700575741a932a64ac99 (diff) | |
soc/intel/common: Implement IOC driver
Starting with Meteor Lake SoC, the PCR/DMI interface to program GPMR
is replaced with IOC (I/O Cache), hence, this patch implements IOC
driver to support that migration.
Reference: 643504 MTL FAS section 7.5.2
TEST=Build and boot to OS for TGL RVP and MTL PSS
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63198
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/pch/lockdown')
| -rw-r--r-- | src/soc/intel/common/pch/lockdown/lockdown.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 42f01bf6d3..f8eb511889 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -30,7 +30,7 @@ int get_lockdown_config(void) static void gpmr_lockdown_cfg(void) { /* - * GCS reg of DMI + * GCS reg * * When set, prevents GCS.BBS from being changed * GCS.BBS: (Boot BIOS Strap) This field determines the destination @@ -43,9 +43,10 @@ static void gpmr_lockdown_cfg(void) /* * Set Secure Register Lock (SRL) bit in DMI control register to lock - * DMI configuration. + * DMI configuration and bypass when IOC instead of DMI */ - gpmr_or32(GPMR_DMICTL, GPMR_DMICTL_SRLOCK); + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)) + gpmr_or32(GPMR_DMICTL, GPMR_DMICTL_SRLOCK); } static void fast_spi_lockdown_cfg(int chipset_lockdown) |