From d107e810c9b188bd313c25638a2878bd4fc61615 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Wed, 1 Sep 2021 23:32:23 -0700 Subject: soc/intel/common: Implement IOC driver Starting with Meteor Lake SoC, the PCR/DMI interface to program GPMR is replaced with IOC (I/O Cache), hence, this patch implements IOC driver to support that migration. Reference: 643504 MTL FAS section 7.5.2 TEST=Build and boot to OS for TGL RVP and MTL PSS Signed-off-by: Wonkyu Kim Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63198 Reviewed-by: Subrata Banik Reviewed-by: Angel Pons Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/common/pch/lockdown/lockdown.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/common/pch/lockdown') diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 42f01bf6d3..f8eb511889 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -30,7 +30,7 @@ int get_lockdown_config(void) static void gpmr_lockdown_cfg(void) { /* - * GCS reg of DMI + * GCS reg * * When set, prevents GCS.BBS from being changed * GCS.BBS: (Boot BIOS Strap) This field determines the destination @@ -43,9 +43,10 @@ static void gpmr_lockdown_cfg(void) /* * Set Secure Register Lock (SRL) bit in DMI control register to lock - * DMI configuration. + * DMI configuration and bypass when IOC instead of DMI */ - gpmr_or32(GPMR_DMICTL, GPMR_DMICTL_SRLOCK); + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)) + gpmr_or32(GPMR_DMICTL, GPMR_DMICTL_SRLOCK); } static void fast_spi_lockdown_cfg(int chipset_lockdown) -- cgit v1.2.3