diff options
author | Subrata Banik <subrata.banik@intel.com> | 2018-05-28 16:12:03 +0530 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-06-07 21:58:19 +0000 |
commit | 9cd99a1524cd8c7cd6100cfc9d68e85eea5ac265 (patch) | |
tree | b5eaea43ae458551051d1f42d952603e60b98d49 /src/soc/intel/common/pch/include | |
parent | 6994bfefb59304140e6b65d4d71e0719b104d257 (diff) |
soc/intel/common/pch: Add pch lockdown code
pch lockdown functionality can be used by supported PCH.
Right now pch lockdown functionality is applied for SPT
(Skylake SOC) and CNP(Cannon Lake SOC) PCH.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL and CNL platform.
Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common/pch/include')
-rw-r--r-- | src/soc/intel/common/pch/include/intelpch/lockdown.h | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/src/soc/intel/common/pch/include/intelpch/lockdown.h b/src/soc/intel/common/pch/include/intelpch/lockdown.h new file mode 100644 index 0000000000..adbf2fe573 --- /dev/null +++ b/src/soc/intel/common/pch/include/intelpch/lockdown.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_PCH_LOCKDOWN_H +#define SOC_INTEL_COMMON_PCH_LOCKDOWN_H + +#include <stdint.h> + +/* + * This function will get lockdown config specific to soc. + * + * Return values: + * 0 = CHIPSET_LOCKDOWN_FSP = use FSP's lockdown functionality to lockdown IPs + * 1 = CHIPSET_LOCKDOWN_COREBOOT = Use coreboot to lockdown IPs + */ +int get_lockdown_config(void); + +/* + * Common PCH lockdown will perform lock down operation for DMI, FAST_SPI. + * And SoC should implement any other PCH lockdown if applicable as + * per silicon security guideline (i.e. LPC, PMC etc.) + * + * Input: + * chipset_lockdown = Return value from get_lockdown_config() function + */ +void soc_lockdown_config(int chipset_lockdown); + +#endif /* SOC_INTEL_COMMON_PCH_LOCKDOWN_H */ |