From 9cd99a1524cd8c7cd6100cfc9d68e85eea5ac265 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 28 May 2018 16:12:03 +0530 Subject: soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../intel/common/pch/include/intelpch/lockdown.h | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 src/soc/intel/common/pch/include/intelpch/lockdown.h (limited to 'src/soc/intel/common/pch/include') diff --git a/src/soc/intel/common/pch/include/intelpch/lockdown.h b/src/soc/intel/common/pch/include/intelpch/lockdown.h new file mode 100644 index 0000000000..adbf2fe573 --- /dev/null +++ b/src/soc/intel/common/pch/include/intelpch/lockdown.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_PCH_LOCKDOWN_H +#define SOC_INTEL_COMMON_PCH_LOCKDOWN_H + +#include + +/* + * This function will get lockdown config specific to soc. + * + * Return values: + * 0 = CHIPSET_LOCKDOWN_FSP = use FSP's lockdown functionality to lockdown IPs + * 1 = CHIPSET_LOCKDOWN_COREBOOT = Use coreboot to lockdown IPs + */ +int get_lockdown_config(void); + +/* + * Common PCH lockdown will perform lock down operation for DMI, FAST_SPI. + * And SoC should implement any other PCH lockdown if applicable as + * per silicon security guideline (i.e. LPC, PMC etc.) + * + * Input: + * chipset_lockdown = Return value from get_lockdown_config() function + */ +void soc_lockdown_config(int chipset_lockdown); + +#endif /* SOC_INTEL_COMMON_PCH_LOCKDOWN_H */ -- cgit v1.2.3