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authorJulien Viard de Galbert <jviarddegalbert@online.net>2018-08-14 16:15:26 +0200
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2018-09-14 14:11:03 +0000
commit2912e8e5dc66708703db79df87e3215408a653ae (patch)
treece3fd68f9114c4654957e4810f273625a148442f /src/soc/intel/common/block
parent86b8d176e8b2d62c1d4a713f91b5858b5d39dd84 (diff)
soc/intel/denverton_ns: Enable common block PMC
Mainly update headers to build. Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove function configuring the global reset through PMC base. On denverton the global reset lock is not in PMC base but in the PCI registers so this code cannot be shared. Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/25426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block')
-rw-r--r--src/soc/intel/common/block/pmc/Kconfig8
-rw-r--r--src/soc/intel/common/block/pmc/pmclib.c2
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig
index 46f134e3b1..2f0840847b 100644
--- a/src/soc/intel/common/block/pmc/Kconfig
+++ b/src/soc/intel/common/block/pmc/Kconfig
@@ -37,3 +37,11 @@ config PMC_INVALID_READ_AFTER_WRITE
help
Enable this for PMC devices where a read back of ACPI BAR and
IO access bit does not return the previously written value.
+
+config PMC_GLOBAL_RESET_ENABLE_LOCK
+ bool
+ help
+ Enable this for PMC devices where the reset configuration
+ and lock register is located under PMC BASE at offset ETR.
+ Note that the reset register is still at 0xCF9 this only
+ controls the enable and lock feature.
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index 339e674a6e..52bfaecd3d 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -419,6 +419,7 @@ int pmc_fill_power_state(struct chipset_power_state *ps)
return ps->prev_sleep_state;
}
+#if IS_ENABLED(CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK)
/*
* If possible, lock 0xcf9. Once the register is locked, it can't be changed.
* This lock is reset on cold boot, hard reset, soft reset and Sx.
@@ -451,6 +452,7 @@ void pmc_global_reset_enable(bool enable)
reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST;
write32((void *)etr, reg);
}
+#endif // CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK
int vboot_platform_is_resuming(void)
{