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-rw-r--r--src/soc/intel/common/block/pmc/Kconfig8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig
index 46f134e3b1..2f0840847b 100644
--- a/src/soc/intel/common/block/pmc/Kconfig
+++ b/src/soc/intel/common/block/pmc/Kconfig
@@ -37,3 +37,11 @@ config PMC_INVALID_READ_AFTER_WRITE
help
Enable this for PMC devices where a read back of ACPI BAR and
IO access bit does not return the previously written value.
+
+config PMC_GLOBAL_RESET_ENABLE_LOCK
+ bool
+ help
+ Enable this for PMC devices where the reset configuration
+ and lock register is located under PMC BASE at offset ETR.
+ Note that the reset register is still at 0xCF9 this only
+ controls the enable and lock feature.