sb,soc/intel: Address TCO SECOND_TO_STS name collision

Later soc/intel/common/smbus addresses TCO2_STS as a separate
16-bit register, while baytrail and braswell assumes 32-bit
wide TCO1_STS to extend as TCO2_STS.

In src/soc/intel/denverton_ns:
  #define TCO2_STS_SECOND_TO 0x02

In soc/intel/baytrail,braswell:
  #define SECOND_TO_STS (1 << 17)

Elsewehere
  #define SECOND_TO_STS (1 << 1)

It's expected that we remove the first (1 << 17) case and only
access TCO2_STS as a separate 16-bit register. For now, use
unique names to avoid confusion.

Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c
index 1ca88428ba..12b176c094 100644
--- a/src/soc/intel/common/block/smbus/tco.c
+++ b/src/soc/intel/common/block/smbus/tco.c
@@ -72,7 +72,7 @@ uint32_t tco_reset_status(void)
 
 	/* TCO Status 2 register */
 	tco2_sts = tco_read_reg(TCO2_STS);
-	tco_write_reg(TCO2_STS, tco2_sts | TCO_STS_SECOND_TO);
+	tco_write_reg(TCO2_STS, tco2_sts | TCO2_STS_SECOND_TO);
 
 	return (tco2_sts << 16) | tco1_sts;
 }