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authorKyösti Mälkki <kyosti.malkki@gmail.com>2022-11-21 17:27:07 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2022-11-28 10:09:04 +0000
commit307320c23f2c1907ff6cf6fa87608d1155aba05f (patch)
tree0db8940fa8deebb85c400c59d5425ebec2b8bf1e /src/soc
parente8a3af10691a4831a85d8760f7fcb20f78065f78 (diff)
sb,soc/intel: Address TCO SECOND_TO_STS name collision
Later soc/intel/common/smbus addresses TCO2_STS as a separate 16-bit register, while baytrail and braswell assumes 32-bit wide TCO1_STS to extend as TCO2_STS. In src/soc/intel/denverton_ns: #define TCO2_STS_SECOND_TO 0x02 In soc/intel/baytrail,braswell: #define SECOND_TO_STS (1 << 17) Elsewehere #define SECOND_TO_STS (1 << 1) It's expected that we remove the first (1 << 17) case and only access TCO2_STS as a separate 16-bit register. For now, use unique names to avoid confusion. Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/alderlake/elog.c2
-rw-r--r--src/soc/intel/apollolake/include/soc/smbus.h2
-rw-r--r--src/soc/intel/baytrail/elog.c2
-rw-r--r--src/soc/intel/baytrail/include/soc/pm.h2
-rw-r--r--src/soc/intel/braswell/elog.c2
-rw-r--r--src/soc/intel/braswell/include/soc/pm.h2
-rw-r--r--src/soc/intel/cannonlake/elog.c2
-rw-r--r--src/soc/intel/common/block/smbus/tco.c2
-rw-r--r--src/soc/intel/common/pch/include/intelpch/smbus.h2
-rw-r--r--src/soc/intel/icelake/elog.c2
-rw-r--r--src/soc/intel/jasperlake/elog.c2
-rw-r--r--src/soc/intel/meteorlake/elog.c2
-rw-r--r--src/soc/intel/skylake/elog.c2
-rw-r--r--src/soc/intel/tigerlake/elog.c2
-rw-r--r--src/soc/intel/xeon_sp/include/soc/smbus.h2
15 files changed, 15 insertions, 15 deletions
diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c
index 7f79d94988..b87130fa82 100644
--- a/src/soc/intel/alderlake/elog.c
+++ b/src/soc/intel/alderlake/elog.c
@@ -170,7 +170,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
/* TCO Timeout */
if (ps->prev_sleep_state != ACPI_S3 &&
- ps->tco2_sts & TCO_STS_SECOND_TO)
+ ps->tco2_sts & TCO2_STS_SECOND_TO)
elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */
diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h
index e11119c485..a87211a6be 100644
--- a/src/soc/intel/apollolake/include/soc/smbus.h
+++ b/src/soc/intel/apollolake/include/soc/smbus.h
@@ -7,7 +7,7 @@
#define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
-#define TCO_STS_SECOND_TO (1 << 1)
+#define TCO2_STS_SECOND_TO (1 << 1)
#define TCO_INTRD_DET (1 << 0)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c
index f732fabc0f..ecdbfca709 100644
--- a/src/soc/intel/baytrail/elog.c
+++ b/src/soc/intel/baytrail/elog.c
@@ -22,7 +22,7 @@ static void log_power_and_resets(const struct chipset_power_state *ps)
if (ps->gen_pmcon1 & RPS)
elog_add_event(ELOG_TYPE_RTC_RESET);
- if (ps->tco_sts & SECOND_TO_STS)
+ if (ps->tco_sts & TCO1_32_STS_SECOND_TO_STS)
elog_add_event(ELOG_TYPE_TCO_RESET);
if (ps->pm1_sts & PRBTNOR_STS)
diff --git a/src/soc/intel/baytrail/include/soc/pm.h b/src/soc/intel/baytrail/include/soc/pm.h
index 1db5038673..515410594b 100644
--- a/src/soc/intel/baytrail/include/soc/pm.h
+++ b/src/soc/intel/baytrail/include/soc/pm.h
@@ -226,7 +226,7 @@
#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
#define TCO_RLD 0x60
#define TCO_STS 0x64
-# define SECOND_TO_STS (1 << 17)
+# define TCO1_32_STS_SECOND_TO_STS (1 << 17)
# define TCO_TIMEOUT (1 << 3)
#define TCO1_CNT 0x68
# define TCO_LOCK (1 << 12)
diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c
index f732fabc0f..ecdbfca709 100644
--- a/src/soc/intel/braswell/elog.c
+++ b/src/soc/intel/braswell/elog.c
@@ -22,7 +22,7 @@ static void log_power_and_resets(const struct chipset_power_state *ps)
if (ps->gen_pmcon1 & RPS)
elog_add_event(ELOG_TYPE_RTC_RESET);
- if (ps->tco_sts & SECOND_TO_STS)
+ if (ps->tco_sts & TCO1_32_STS_SECOND_TO_STS)
elog_add_event(ELOG_TYPE_TCO_RESET);
if (ps->pm1_sts & PRBTNOR_STS)
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h
index 131a996919..b918577646 100644
--- a/src/soc/intel/braswell/include/soc/pm.h
+++ b/src/soc/intel/braswell/include/soc/pm.h
@@ -188,7 +188,7 @@
#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
#define TCO_RLD 0x60
#define TCO_STS 0x64
-# define SECOND_TO_STS (1 << 17)
+# define TCO1_32_STS_SECOND_TO_STS (1 << 17)
# define TCO_TIMEOUT (1 << 3)
#define TCO1_CNT 0x68
# define TCO_LOCK (1 << 12)
diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c
index dcc1a798cd..f8d06511d1 100644
--- a/src/soc/intel/cannonlake/elog.c
+++ b/src/soc/intel/cannonlake/elog.c
@@ -135,7 +135,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
/* TCO Timeout */
if (ps->prev_sleep_state != ACPI_S3 &&
- ps->tco2_sts & TCO_STS_SECOND_TO)
+ ps->tco2_sts & TCO2_STS_SECOND_TO)
elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */
diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c
index 1ca88428ba..12b176c094 100644
--- a/src/soc/intel/common/block/smbus/tco.c
+++ b/src/soc/intel/common/block/smbus/tco.c
@@ -72,7 +72,7 @@ uint32_t tco_reset_status(void)
/* TCO Status 2 register */
tco2_sts = tco_read_reg(TCO2_STS);
- tco_write_reg(TCO2_STS, tco2_sts | TCO_STS_SECOND_TO);
+ tco_write_reg(TCO2_STS, tco2_sts | TCO2_STS_SECOND_TO);
return (tco2_sts << 16) | tco1_sts;
}
diff --git a/src/soc/intel/common/pch/include/intelpch/smbus.h b/src/soc/intel/common/pch/include/intelpch/smbus.h
index 238da2b73b..78b7953950 100644
--- a/src/soc/intel/common/pch/include/intelpch/smbus.h
+++ b/src/soc/intel/common/pch/include/intelpch/smbus.h
@@ -7,7 +7,7 @@
#define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
-#define TCO_STS_SECOND_TO (1 << 1)
+#define TCO2_STS_SECOND_TO (1 << 1)
#define TCO_INTRD_DET (1 << 0)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
diff --git a/src/soc/intel/icelake/elog.c b/src/soc/intel/icelake/elog.c
index 4967fde001..01f133ac86 100644
--- a/src/soc/intel/icelake/elog.c
+++ b/src/soc/intel/icelake/elog.c
@@ -70,7 +70,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
/* TCO Timeout */
if (ps->prev_sleep_state != ACPI_S3 &&
- ps->tco2_sts & TCO_STS_SECOND_TO)
+ ps->tco2_sts & TCO2_STS_SECOND_TO)
elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */
diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c
index 0e4b2c5149..f42e06c81f 100644
--- a/src/soc/intel/jasperlake/elog.c
+++ b/src/soc/intel/jasperlake/elog.c
@@ -143,7 +143,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
/* TCO Timeout */
if (ps->prev_sleep_state != ACPI_S3 &&
- ps->tco2_sts & TCO_STS_SECOND_TO)
+ ps->tco2_sts & TCO2_STS_SECOND_TO)
elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */
diff --git a/src/soc/intel/meteorlake/elog.c b/src/soc/intel/meteorlake/elog.c
index 35100f9ad1..14d086c38d 100644
--- a/src/soc/intel/meteorlake/elog.c
+++ b/src/soc/intel/meteorlake/elog.c
@@ -173,7 +173,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
/* TCO Timeout */
if (ps->prev_sleep_state != ACPI_S3 &&
- ps->tco2_sts & TCO_STS_SECOND_TO)
+ ps->tco2_sts & TCO2_STS_SECOND_TO)
elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */
diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c
index 1761671e67..325bacb0f3 100644
--- a/src/soc/intel/skylake/elog.c
+++ b/src/soc/intel/skylake/elog.c
@@ -202,7 +202,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
/* TCO Timeout */
if (ps->prev_sleep_state != ACPI_S3 &&
- ps->tco2_sts & TCO_STS_SECOND_TO)
+ ps->tco2_sts & TCO2_STS_SECOND_TO)
elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */
diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c
index 29f1712eeb..650d1cd4c8 100644
--- a/src/soc/intel/tigerlake/elog.c
+++ b/src/soc/intel/tigerlake/elog.c
@@ -178,7 +178,7 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
/* TCO Timeout */
if (ps->prev_sleep_state != ACPI_S3 &&
- ps->tco2_sts & TCO_STS_SECOND_TO)
+ ps->tco2_sts & TCO2_STS_SECOND_TO)
elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */
diff --git a/src/soc/intel/xeon_sp/include/soc/smbus.h b/src/soc/intel/xeon_sp/include/soc/smbus.h
index 00aae2cbe8..7ef9d0b2d1 100644
--- a/src/soc/intel/xeon_sp/include/soc/smbus.h
+++ b/src/soc/intel/xeon_sp/include/soc/smbus.h
@@ -7,7 +7,7 @@
#define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
-#define TCO_STS_SECOND_TO (1 << 1)
+#define TCO2_STS_SECOND_TO (1 << 1)
#define TCO_INTRD_DET (1 << 0)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 19:26:02 +0000