diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-08-04 16:04:46 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-08-10 16:25:00 +0000 |
| commit | 3b90b5f1299053e87e718501f6c9be50dd343686 (patch) | |
| tree | 83de8b47726cd3b61eb14d17b23dd78630b3eff1 /src/soc/intel/common/block/lpss | |
| parent | 3406dd64c328bf0f2f1902d42b239f84c136e4f0 (diff) | |
soc/intel/common/lpss: Add lpss_is_controller_in_reset
Add new API function lpss_is_controller_in_reset that returns whether
the LPSS controller is in reset. Also, add lpss.c to smm stage so that
lpss_is_controller_in_reset can be used in smihandler.
BUG=b:64030366
Change-Id: I0fe5c2890ee799b08482e487296a483fa8d42461
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/lpss')
| -rw-r--r-- | src/soc/intel/common/block/lpss/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/lpss/lpss.c | 11 |
2 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/lpss/Makefile.inc b/src/soc/intel/common/block/lpss/Makefile.inc index 50d1c10850..6ed654f750 100644 --- a/src/soc/intel/common/block/lpss/Makefile.inc +++ b/src/soc/intel/common/block/lpss/Makefile.inc @@ -2,3 +2,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 146fdab2ed..feacef370f 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -39,6 +39,17 @@ /* DMA Software Reset Control */ #define LPSS_DMA_RST_RELEASE (1 << 2) +bool lpss_is_controller_in_reset(uintptr_t base) +{ + uint8_t *addr = (void *)base; + uint32_t val = read32(addr + LPSS_RESET_CTL_REG); + + if (val == 0xFFFFFFFF) + return true; + + return !(val & LPSS_CNT_RST_RELEASE); +} + void lpss_reset_release(uintptr_t base) { uint8_t *addr = (void *)base; |