diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-04-14 00:08:05 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-04-19 05:46:11 +0000 |
| commit | d5e7c63a85136d1679c709da98bc80bd819663ed (patch) | |
| tree | 42e96cf555ad3622811cb3f93f44198efc49c2d8 /src/soc/intel/common/block/fast_spi | |
| parent | a26bb7878bd8728b43887ebee7dc86f658a35109 (diff) | |
soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status
This patch creates a helper function to clear HSFSTS_CTL (offset 0x04)
register Bits 0 to 4.
As per Intel PCH BIOS spec section 3.6 Flash Security Recommendation,
it's important to clear all SPI outstanding status before setting SPI
lock bits.
BUG=b:211954778
TEST=Able to build google/brya with this patch and clear SPI controller
HSFSTS_CTL register Bits 0 to 4.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I62adba0d0cef1d4c53b24800f90b4fe76a9d78b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/common/block/fast_spi')
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/fast_spi.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 5a76df3d37..4ff1e9ba70 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -428,3 +428,11 @@ void fast_spi_disable_wp(void) bios_cntl |= SPI_BIOS_CONTROL_WPD; pci_write_config8(dev, SPI_BIOS_CONTROL, bios_cntl); } + +void fast_spi_clear_outstanding_status(void) +{ + void *spibar = fast_spi_get_bar(); + + /* Make sure all W1C status bits get cleared. */ + write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS); +} |