From d5e7c63a85136d1679c709da98bc80bd819663ed Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 14 Apr 2022 00:08:05 +0530 Subject: soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch creates a helper function to clear HSFSTS_CTL (offset 0x04) register Bits 0 to 4. As per Intel PCH BIOS spec section 3.6 Flash Security Recommendation, it's important to clear all SPI outstanding status before setting SPI lock bits. BUG=b:211954778 TEST=Able to build google/brya with this patch and clear SPI controller HSFSTS_CTL register Bits 0 to 4. Signed-off-by: Subrata Banik Change-Id: I62adba0d0cef1d4c53b24800f90b4fe76a9d78b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63625 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/soc/intel/common/block/fast_spi/fast_spi.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/soc/intel/common/block/fast_spi') diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 5a76df3d37..4ff1e9ba70 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -428,3 +428,11 @@ void fast_spi_disable_wp(void) bios_cntl |= SPI_BIOS_CONTROL_WPD; pci_write_config8(dev, SPI_BIOS_CONTROL, bios_cntl); } + +void fast_spi_clear_outstanding_status(void) +{ + void *spibar = fast_spi_get_bar(); + + /* Make sure all W1C status bits get cleared. */ + write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS); +} -- cgit v1.2.3