diff options
| author | Cliff Huang <cliff.huang@intel.com> | 2024-08-21 18:02:14 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-09-05 07:53:10 +0000 |
| commit | 1ef8da2f5bc36c5a9276e25d5ff0f7ce4b6a5d19 (patch) | |
| tree | 259b9e85960e475c9a20b777f499d17f8ab2c82a /src/soc/intel/common/block/acpi/Kconfig | |
| parent | 640d1c456c977711774f0b7f58f1a97e4512fc4b (diff) | |
soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to enable GPE1 block.
This will include GPE1 blocks to FADT with their info.
BUG=362310295
TEST=boot to OS and check that FADT table include GPE1.
FADT should have:
GPE1 Block Address : 00001810
GPE1 Block Length : 18
GPE1 Base Offset : 80
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84103
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/acpi/Kconfig')
| -rw-r--r-- | src/soc/intel/common/block/acpi/Kconfig | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 36b47a3c4f..459a95285a 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -76,4 +76,16 @@ config SOC_INTEL_COMMON_BLOCK_ACPI_SLP_S0_FREQ_HZ Define the slp_s0_residency frequency to be reported in the LPIT ACPI table. +config SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 + bool "Use GPE1 Event bits" + help + Include GPE1 STS and EN registers in FADT. Requires define GPE1_STS(0) + and GPE1_REG_MAX from the SOC header. The SOC needs to have GPE1 block + implemented to select this. This flag will also be used to determine the + standard GPE0/1 event methods to use in the ASL code or devicetree for the + internal wake capable devices. GPE1 Event Bit is an extension of GPE0 + (present in all Intel SoC platform). GPE1 Events include the power + management, hot plug, and PCIe events for the internal devices. Select + this Kconfig to support SoCs that publish GPE1 as part of PMC IO register. + endif |