soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table

Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to enable GPE1 block.
This will include GPE1 blocks to FADT with their info.

BUG=362310295
TEST=boot to OS and check that FADT table include GPE1.
FADT should have:
GPE1 Block Address : 00001810
GPE1 Block Length : 18
GPE1 Base Offset : 80

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84103
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 35 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig
index 36b47a3c4f..459a95285a 100644
--- a/src/soc/intel/common/block/acpi/Kconfig
+++ b/src/soc/intel/common/block/acpi/Kconfig
@@ -76,4 +76,16 @@ config SOC_INTEL_COMMON_BLOCK_ACPI_SLP_S0_FREQ_HZ
 	  Define the slp_s0_residency frequency to be reported in the
 	  LPIT ACPI table.
 
+config SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1
+	bool "Use GPE1 Event bits"
+	help
+	  Include GPE1 STS and EN registers in FADT. Requires define GPE1_STS(0)
+	  and GPE1_REG_MAX from the SOC header. The SOC needs to have GPE1 block
+	  implemented to select this. This flag will also be used to determine the
+	  standard GPE0/1 event methods to use in the ASL code or devicetree for the
+	  internal wake capable devices. GPE1 Event Bit is an extension of GPE0
+	  (present in all Intel SoC platform). GPE1 Events include the power
+	  management, hot plug, and PCIe events for the internal devices. Select
+	  this Kconfig to support SoCs that publish GPE1 as part of PMC IO register.
+
 endif
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index 1faf433113..dcd4dc4cca 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -107,6 +107,16 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	/* GPE0 STS/EN pairs each 32 bits wide. */
 	fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
 
+	fadt->gpe1_blk = GPE1_STS(0) ? (pmbase + GPE1_STS(0)) : 0;
+	if (fadt->gpe1_blk) {
+		fadt->gpe1_blk_len = 2 * GPE1_REG_MAX * sizeof(uint32_t);
+		/*
+		 * NOTE: gpe1 is after gpe0, which has _STS and _EN register sets.
+		 * gpe1_base is the starting bit offset for GPE1.
+		 */
+		fadt->gpe1_base = fadt->gpe0_blk_len / 2 * 8;
+	}
+
 	fill_fadt_extended_pm_io(fadt);
 
 	fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h
index fd61489431..18d1b4d234 100644
--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h
+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h
@@ -8,6 +8,19 @@
 
 #define PCH_PMC_EPOC			0x18EC
 
+/*
+ * GPE1 support is introduced in PTL. The existing standard GPE
+ * functions will cover GPE1 when SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is
+ * selected. In addition, the following SOC GPE1 defines are required in common
+ * code but not present in older platform headers. Therefore, the dummy entries
+ * are added here for platforms without GPE1 support.
+ */
+#if !CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1)
+#define GPE1_STS(x) (0x0 + ((x) * 4))
+#define GPE1_EN(x) (0x0 + ((x) * 4))
+#define GPE1_REG_MAX 0
+#endif
+
 /**
  * enum pch_pmc_xtal - External crystal oscillator frequency.
  * @XTAL_24_MHZ: 24 MHz external crystal.