diff options
| author | Shaunak Saha <shaunak.saha@intel.com> | 2017-10-04 23:08:40 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-26 15:55:37 +0000 |
| commit | 95b61752dbb56b9a7a2da439c5d21e30643661ef (patch) | |
| tree | b7856619ddeb70752c935f727a46f9779f8dae0d /src/soc/intel/cannonlake/include | |
| parent | 66b5acc54bf75b186efea431dfac6eebce527403 (diff) | |
soc/intel/cannonlake: Add support for C state and P state
This patch adds the C state and P state configurations for
cannonlake soc.
TEST = Boot and test the CPU states for all the cores are
present in "powertop" tool output.
Change-Id: I4ba156354f87646b25d0f9114ebf0583eedf72df
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h index 866f7588d2..bd9db37848 100644 --- a/src/soc/intel/cannonlake/include/soc/cpu.h +++ b/src/soc/intel/cannonlake/include/soc/cpu.h @@ -19,6 +19,7 @@ #include <arch/cpu.h> #include <device/device.h> +#include <intelblocks/msr.h> /* Supported CPUIDs */ #define CPUID_CANNONLAKE_A0 0x60660 @@ -35,7 +36,6 @@ /* Power in units of mW */ #define C1_POWER 0x3e8 -#define C3_POWER 0x1f4 #define C6_POWER 0x15e #define C7_POWER 0xc8 #define C8_POWER 0xc8 |