From 95b61752dbb56b9a7a2da439c5d21e30643661ef Mon Sep 17 00:00:00 2001
From: Shaunak Saha <shaunak.saha@intel.com>
Date: Wed, 4 Oct 2017 23:08:40 -0700
Subject: soc/intel/cannonlake: Add support for C state and P state

This patch adds the C state and P state configurations for
cannonlake soc.

TEST = Boot and test the CPU states for all the cores are
       present in "powertop" tool output.

Change-Id: I4ba156354f87646b25d0f9114ebf0583eedf72df
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/cannonlake/include/soc/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/soc/intel/cannonlake/include')

diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h
index 866f7588d2..bd9db37848 100644
--- a/src/soc/intel/cannonlake/include/soc/cpu.h
+++ b/src/soc/intel/cannonlake/include/soc/cpu.h
@@ -19,6 +19,7 @@
 
 #include <arch/cpu.h>
 #include <device/device.h>
+#include <intelblocks/msr.h>
 
 /* Supported CPUIDs */
 #define CPUID_CANNONLAKE_A0	0x60660
@@ -35,7 +36,6 @@
 
 /* Power in units of mW */
 #define C1_POWER	0x3e8
-#define C3_POWER	0x1f4
 #define C6_POWER	0x15e
 #define C7_POWER	0xc8
 #define C8_POWER	0xc8
-- 
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