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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-08-26 09:17:53 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-09-05 19:20:19 +0000
commit9f0266c599d3a54c9a74d32063ac6723f3d147a6 (patch)
treeb4ea1a376a6fba8cecfa7f58af43968e8de1f9ea /src/soc/intel/cannonlake/finalize.c
parent9ed175167664b63beb19cb656b53cbf6033f6a75 (diff)
soc/intel/cannonlake: Lock PAM registers in finalize
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: I6ae22f9df4834508dfa304050fad44d45df45334 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/finalize.c')
-rw-r--r--src/soc/intel/cannonlake/finalize.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index 8888315747..63749f92cf 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -10,8 +10,10 @@
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h>
+#include <intelblocks/systemagent.h>
#include <intelblocks/tco.h>
#include <intelblocks/thermal.h>
+#include <intelpch/lockdown.h>
#include <soc/p2sb.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
@@ -80,12 +82,19 @@ static void pch_finalize(void)
}
+static void sa_finalize(void)
+{
+ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
+ sa_lock_pam();
+}
+
static void soc_finalize(void *unused)
{
printk(BIOS_DEBUG, "Finalizing chipset.\n");
pch_finalize();
apm_control(APM_CNT_FINALIZE);
+ sa_finalize();
/* Indicate finalize step with post code */
post_code(POST_OS_BOOT);