diff options
| -rw-r--r-- | src/soc/intel/cannonlake/finalize.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 1 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 8888315747..63749f92cf 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -10,8 +10,10 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> +#include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> +#include <intelpch/lockdown.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> @@ -80,12 +82,19 @@ static void pch_finalize(void) } +static void sa_finalize(void) +{ + if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) + sa_lock_pam(); +} + static void soc_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); pch_finalize(); apm_control(APM_CNT_FINALIZE); + sa_finalize(); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dd5f197a19..1ae27aefee 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -653,6 +653,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) tconfig->PchLockDownBiosInterface = lockdown_by_fsp; params->PchLockDownBiosLock = lockdown_by_fsp; params->PchLockDownRtcMemoryLock = lockdown_by_fsp; + tconfig->SkipPamLock = !lockdown_by_fsp; #if CONFIG(SOC_INTEL_COMETLAKE) /* * Making this config "0" means FSP won't set the FLOCKDN bit |