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authorElyes Haouas <ehaouas@noos.fr>2022-11-22 17:36:02 +0100
committerEric Lai <eric_lai@quanta.corp-partner.google.com>2022-11-30 03:07:23 +0000
commit8b8ada6fdb3ebab672571c581eed3a7285589d83 (patch)
treee54135b01dcd48a1c3b3db4e6f16efee8740a2b9 /src/soc/intel/broadwell/pch
parentcc22607dbfbab0c9ce42c071b5b3c4a304845313 (diff)
/: Remove extra space after comma
Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69903 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/pch')
-rw-r--r--src/soc/intel/broadwell/pch/pcie.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c
index b37f256069..61d6962a82 100644
--- a/src/soc/intel/broadwell/pch/pcie.c
+++ b/src/soc/intel/broadwell/pch/pcie.c
@@ -295,7 +295,7 @@ static void root_port_commit_config(void)
if (dev->enabled)
continue;
- printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
+ printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* 8.2 Configuration of PCI Express Root Ports */
pci_or_config32(dev, 0x338, 1 << 26);