diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-11-22 17:36:02 +0100 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2022-11-30 03:07:23 +0000 |
| commit | 8b8ada6fdb3ebab672571c581eed3a7285589d83 (patch) | |
| tree | e54135b01dcd48a1c3b3db4e6f16efee8740a2b9 /src/soc | |
| parent | cc22607dbfbab0c9ce42c071b5b3c4a304845313 (diff) | |
/: Remove extra space after comma
Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69903
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/broadwell/pch/pcie.c | 2 | ||||
| -rw-r--r-- | src/soc/samsung/exynos5420/dp_lowlevel.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index b37f256069..61d6962a82 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -295,7 +295,7 @@ static void root_port_commit_config(void) if (dev->enabled) continue; - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* 8.2 Configuration of PCI Express Root Ports */ pci_or_config32(dev, 0x338, 1 << 26); diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index 0cd64833f4..2d33873a28 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -229,7 +229,7 @@ unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable) CH2_PD | CH3_PD); break; default: - printk(BIOS_ERR, "DP undefined block number : %d\n", block); + printk(BIOS_ERR, "DP undefined block number : %d\n", block); return -1; } |