diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-11-07 12:47:35 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-05-06 18:38:58 +0200 |
| commit | 6aa9f1f0eb97e315ab4db8e6da1d13db7ee7858f (patch) | |
| tree | 7884df6e2008f857bf0cd77a35ed028fd02d02bc /src/soc/intel/baytrail/ramstage.c | |
| parent | 05a3393a2c089d0c7ad7443e2298dacd129fadb3 (diff) | |
baytrail: Add BCLK and IACORE to pattrs
The bus clock speed is needed when building ACPI P-state tables
so extract that function and have the value be saved in pattrs.
The various IACORE values are also needed, but rather than have
the ACPI code to the bit manipulation have the pattrs store an
array of the possible values for it to use directly.
BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi
Change-Id: I5ac06ccf66e9109186dd01342dbb6ccdd334ca69
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176140
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4953
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/ramstage.c')
| -rw-r--r-- | src/soc/intel/baytrail/ramstage.c | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index ab29190936..0c2bed86b7 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -76,6 +76,7 @@ static const char *stepping_str[] = { "A0", "A1", "B0", "B1", "B2", "B3" }; static void fill_in_pattrs(void) { device_t dev; + msr_t msr; struct pattrs *attrs = (struct pattrs *)pattrs_get(); attrs->cpuid = cpuid_eax(1); @@ -103,8 +104,24 @@ static void fill_in_pattrs(void) fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); - fill_in_msr(&attrs->iacore_ratios, MSR_IACORE_RATIOS); - fill_in_msr(&attrs->iacore_vids, MSR_IACORE_VIDS); + + /* Set IA core speed ratio and voltages */ + msr = rdmsr(MSR_IACORE_RATIOS); + attrs->iacore_ratios[IACORE_MIN] = msr.lo & 0x7f; + attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f; + attrs->iacore_ratios[IACORE_MAX] = (msr.lo >> 16) & 0x7f; + msr = rdmsr(MSR_IACORE_TURBO_RATIOS); + attrs->iacore_ratios[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ + + msr = rdmsr(MSR_IACORE_VIDS); + attrs->iacore_vids[IACORE_MIN] = msr.lo & 0x7f; + attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f; + attrs->iacore_vids[IACORE_MAX] = (msr.lo >> 16) & 0x7f; + msr = rdmsr(MSR_IACORE_TURBO_VIDS); + attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ + + /* Set bus clock speed */ + attrs->bclk_khz = bus_freq_khz(); } static inline void set_acpi_sleep_type(int val) |