diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2022-01-08 13:16:38 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-11 14:04:33 +0000 |
| commit | 5e7f90bb4c24ad9c500de153df3b2304f569f6e9 (patch) | |
| tree | 984f5cc644af96a65d570f9a0f14ec5a890c074f /src/soc/intel/alderlake/Kconfig | |
| parent | 29e33551a92368ae69063a8bff1cfd80904918c9 (diff) | |
soc/intel/alderlake: Factor out A0 stepping workaround
Move the `configure_pmc_descriptor()` function to SoC scope instead of
having two identical copies in mainboard scope. Add a Kconfig option to
allow mainboards to decide whether to implement this workaround.
Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake/Kconfig')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 50c0c0b3e5..74c14a5ef6 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -102,6 +102,15 @@ config CPU_SPECIFIC_OPTIONS select UDK_202005_BINDING select DISPLAY_FSP_VERSION_INFO +config ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR + bool + help + Alder Lake stepping A0 needs a different value for a PMC setting in + the IFD. When this option is selected, coreboot will update the IFD + value at runtime, which allows using an IFD with the new value with + any CPU stepping. To apply this workaround, the IFD region needs to + be writable by the host. + config ALDERLAKE_CAR_ENHANCED_NEM bool default y if !INTEL_CAR_NEM |