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author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-02-12 12:24:25 +0100 |
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committer | Martin Roth <martinroth@google.com> | 2018-02-20 23:17:39 +0000 |
commit | 5268b76801280667d8c27619fe2d771569c4e346 (patch) | |
tree | 075fa6b949b6719450755cdcdec912936a6754c2 /src/soc/imgtec/pistachio/ddr2_init.c | |
parent | e33f120cb808b946f3052019c9e4cf54b086491a (diff) |
src/soc: Fix various typos
These typos were found through manual review and grep.
Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/imgtec/pistachio/ddr2_init.c')
-rw-r--r-- | src/soc/imgtec/pistachio/ddr2_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c index 9549537261..aac85a9f20 100644 --- a/src/soc/imgtec/pistachio/ddr2_init.c +++ b/src/soc/imgtec/pistachio/ddr2_init.c @@ -288,7 +288,7 @@ int init_ddr2(void) */ write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x00000012); /* - * TRC : Min. ROW cylce time + * TRC : Min. ROW cycle time * Range 11 to 31: 57.5ns / 2.5ns = 23d Playing safe 24 */ write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000018); |