From 5268b76801280667d8c27619fe2d771569c4e346 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Mon, 12 Feb 2018 12:24:25 +0100 Subject: src/soc: Fix various typos MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These typos were found through manual review and grep. Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/23706 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ronald G. Minnich --- src/soc/imgtec/pistachio/ddr2_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/imgtec/pistachio/ddr2_init.c') diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c index 9549537261..aac85a9f20 100644 --- a/src/soc/imgtec/pistachio/ddr2_init.c +++ b/src/soc/imgtec/pistachio/ddr2_init.c @@ -288,7 +288,7 @@ int init_ddr2(void) */ write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x00000012); /* - * TRC : Min. ROW cylce time + * TRC : Min. ROW cycle time * Range 11 to 31: 57.5ns / 2.5ns = 23d Playing safe 24 */ write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000018); -- cgit v1.2.3