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authorJamie Chen <jamie.chen@intel.com>2022-03-15 16:16:30 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-04-22 21:36:34 +0000
commit5b58902749196787f881dd06bc109cca24dbe073 (patch)
tree4a9d9495c1a210bb2db7a0ed86a3655f0aa38dd1 /src/soc/cavium/cn81xx/gpio.c
parentb30f8687b2a097c85b87b65b392833d43566c9d1 (diff)
soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumption
According to Intel TA#724456, work around the higher SoC power consumption in S0iX when CNVI has background activity. BUG=b:201263040 TEST=Turn on this setting and build and verify on Drawcia. The SLP_S0 toggling become slower or gone at the same CNVI background activity. Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63675 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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