diff options
| -rw-r--r-- | src/soc/intel/jasperlake/chip.h | 13 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/finalize.c | 5 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/include/soc/pmc.h | 5 |
3 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index f3e7240b57..398fe71699 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -421,6 +421,19 @@ struct soc_intel_jasperlake_config { CD_CLOCK_652_8_MHZ = 9, } cd_clock; + /* + * This is a workaround to mitigate higher SoC power consumption in S0ix + * when the CNVI has background activity. + * + * Setting this on a system that supports S0i3 (set xtalsdqdis [Bit 22] in + * cppmvric1 register to 0) will break CNVI timing. + * Affected Intel wireless chipsets: AC9560 (JfP2), AC9461/AC9462 (JfP1) and + * AX201 (HrP2) + * + * true: Enabled (fewer wakes, lower power) + * false: Disabled (more wakes, higher power) + */ + bool cnvi_reduce_s0ix_pwr_usage; }; typedef struct soc_intel_jasperlake_config config_t; diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index a3d4328e6b..3b0d49742e 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -59,6 +59,11 @@ static void pch_finalize(void) reg32 = read32(pmcbase + CPPMVRIC3); reg32 &= ~USBSUSPGQDIS; write32(pmcbase + CPPMVRIC3, reg32); + + if (config->cnvi_reduce_s0ix_pwr_usage) { + setbits32(pmcbase + CPPMVRIC2, CNVIVNNAONREQQDIS); + setbits32(pmcbase + CORE_SPARE_GCR_0, BIT(0)); + } } pch_handle_sideband(config); diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h index 1df2c63ab8..1922657810 100644 --- a/src/soc/intel/jasperlake/include/soc/pmc.h +++ b/src/soc/intel/jasperlake/include/soc/pmc.h @@ -121,9 +121,14 @@ #define SLP_S0_RES 0x193c +#define CORE_SPARE_GCR_0 0x195C + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) +#define CPPMVRIC2 0x1B4C +#define CNVIVNNAONREQQDIS (1 << 26) + #define CPPMVRIC3 0x1E4C #define USBSUSPGQDIS (1 << 15) |