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authorAngel Pons <th3fanbus@gmail.com>2021-06-22 15:18:07 +0200
committerAngel Pons <th3fanbus@gmail.com>2021-07-02 08:19:10 +0000
commit6f5a6581a61706b0b271ff16845fd0cefe46928b (patch)
tree53d856256dd67a3675f4f445245d4b0fe8f0672e /src/soc/amd
parentde62f55507b6ca4f98df3edd75b57e73814c1f2d (diff)
src: Introduce `ARCH_ALL_STAGES_X86`
Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically select the per-stage arch options. Subsequent commits will leverage this to allow choosing between 32-bit and 64-bit coreboot where all stages are x86. AMD Picasso and AMD Cezanne are the only exceptions to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set the per-stage arch options accordingly. Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/cezanne/Kconfig3
-rw-r--r--src/soc/amd/picasso/Kconfig3
-rw-r--r--src/soc/amd/stoneyridge/Kconfig1
3 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 78db12fc70..7dd3447234 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -70,6 +70,9 @@ config SOC_SPECIFIC_OPTIONS
select X86_AMD_FIXED_MTRRS
select X86_AMD_INIT_SIPI
+config ARCH_ALL_STAGES_X86
+ default n
+
config SOC_AMD_COMMON_BLOCK_UCODE_SIZE
default 5568
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 44728a8a80..42c3bfc029 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -69,6 +69,9 @@ config CPU_SPECIFIC_OPTIONS
select UDK_2017_BINDING
select HAVE_CF9_RESET
+config ARCH_ALL_STAGES_X86
+ default n
+
config SOC_AMD_COMMON_BLOCK_UCODE_SIZE
default 3200
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 0e80f14fc4..821d1ee216 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -10,7 +10,6 @@ if SOC_AMD_STONEYRIDGE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_SOC_NVS
- select ARCH_ALL_STAGES_X86_32
select ARCH_X86
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
select COLLECT_TIMESTAMPS_NO_TSC