soc/amd/*/include/msr: add version number to SERIAL_VID_* define names

Picasso and Cezanne use the serial voltage ID 2 standard to communicate
the CPU voltage to the voltage regulator module on the mainboard, while
Mendocino, Phoenix and Glinda use the serial voltage ID 3 standard for
this. Both standards encode the voltage in a different way, so add the
serial VID version number to the defines to clarify for which version
the define is.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8ddab8df27c86dc2c70a6dfb47908d9405d86240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73994
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>

10 files changed, 20 insertions, 20 deletions

diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c
index f65973d979..43ed7fed05 100644
--- a/src/soc/amd/cezanne/acpi.c
+++ b/src/soc/amd/cezanne/acpi.c
@@ -150,8 +150,8 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
 		/* Voltage off for VID codes 0xF8 to 0xFF */
 		voltage_in_uvolts = 0;
 	} else {
-		voltage_in_uvolts =
-			SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
+		voltage_in_uvolts = SERIAL_VID_2_MAX_MICROVOLTS -
+					(SERIAL_VID_2_DECODE_MICROVOLTS * core_vid);
 	}
 
 	/* Power in mW */
diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h
index 2ce03ade8a..fdbe47e342 100644
--- a/src/soc/amd/cezanne/include/soc/msr.h
+++ b/src/soc/amd/cezanne/include/soc/msr.h
@@ -23,8 +23,8 @@ union pstate_msr {
 #define PSTATE_DEF_CORE_FREQ_BASE	25
 
 /* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */
-#define  SERIAL_VID_DECODE_MICROVOLTS	6250
-#define  SERIAL_VID_MAX_MICROVOLTS	1550000L
+#define  SERIAL_VID_2_DECODE_MICROVOLTS	6250
+#define  SERIAL_VID_2_MAX_MICROVOLTS	1550000L
 
 #define MSR_CPPC_CAPABILITY_1				0xc00102b0
 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF		24
diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c
index 1accc962d4..37349c15ae 100644
--- a/src/soc/amd/glinda/acpi.c
+++ b/src/soc/amd/glinda/acpi.c
@@ -127,8 +127,8 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
 		/* Voltage off for VID code 0x00 */
 		voltage_in_uvolts = 0;
 	} else {
-		voltage_in_uvolts =
-			SERIAL_VID_BASE_MICROVOLTS + (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
+		voltage_in_uvolts = SERIAL_VID_3_BASE_MICROVOLTS +
+					(SERIAL_VID_3_DECODE_MICROVOLTS * core_vid);
 	}
 
 	/* Power in mW */
diff --git a/src/soc/amd/glinda/include/soc/msr.h b/src/soc/amd/glinda/include/soc/msr.h
index 3f9254971c..7b6889709e 100644
--- a/src/soc/amd/glinda/include/soc/msr.h
+++ b/src/soc/amd/glinda/include/soc/msr.h
@@ -23,8 +23,8 @@ union pstate_msr {
 #define PSTATE_DEF_CORE_FREQ_BASE	5
 
 /* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
-#define  SERIAL_VID_DECODE_MICROVOLTS	5000
-#define  SERIAL_VID_BASE_MICROVOLTS	245000L
+#define  SERIAL_VID_3_DECODE_MICROVOLTS	5000
+#define  SERIAL_VID_3_BASE_MICROVOLTS	245000L
 
 #define MSR_CPPC_CAPABILITY_1				0xc00102b0
 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF		24
diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c
index 5bc893c458..f6a95bf565 100644
--- a/src/soc/amd/mendocino/acpi.c
+++ b/src/soc/amd/mendocino/acpi.c
@@ -152,8 +152,8 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
 		/* Voltage off for VID code 0x00 */
 		voltage_in_uvolts = 0;
 	} else {
-		voltage_in_uvolts =
-			SERIAL_VID_BASE_MICROVOLTS + (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
+		voltage_in_uvolts = SERIAL_VID_3_BASE_MICROVOLTS +
+					(SERIAL_VID_3_DECODE_MICROVOLTS * core_vid);
 	}
 
 	/* Power in mW */
diff --git a/src/soc/amd/mendocino/include/soc/msr.h b/src/soc/amd/mendocino/include/soc/msr.h
index f8e6092afe..cb03425d2a 100644
--- a/src/soc/amd/mendocino/include/soc/msr.h
+++ b/src/soc/amd/mendocino/include/soc/msr.h
@@ -24,8 +24,8 @@ union pstate_msr {
 #define PSTATE_DEF_CORE_FREQ_BASE	25
 
 /* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
-#define  SERIAL_VID_DECODE_MICROVOLTS	5000
-#define  SERIAL_VID_BASE_MICROVOLTS	245000L
+#define  SERIAL_VID_3_DECODE_MICROVOLTS	5000
+#define  SERIAL_VID_3_BASE_MICROVOLTS	245000L
 
 #define MSR_CPPC_CAPABILITY_1				0xc00102b0
 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF		24
diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c
index 4fae1c9d74..e3996ba869 100644
--- a/src/soc/amd/phoenix/acpi.c
+++ b/src/soc/amd/phoenix/acpi.c
@@ -153,8 +153,8 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
 		/* Voltage off for VID code 0x00 */
 		voltage_in_uvolts = 0;
 	} else {
-		voltage_in_uvolts =
-			SERIAL_VID_BASE_MICROVOLTS + (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
+		voltage_in_uvolts = SERIAL_VID_3_BASE_MICROVOLTS +
+					(SERIAL_VID_3_DECODE_MICROVOLTS * core_vid);
 	}
 
 	/* Power in mW */
diff --git a/src/soc/amd/phoenix/include/soc/msr.h b/src/soc/amd/phoenix/include/soc/msr.h
index ef7a2e2260..8eee0683ae 100644
--- a/src/soc/amd/phoenix/include/soc/msr.h
+++ b/src/soc/amd/phoenix/include/soc/msr.h
@@ -26,8 +26,8 @@ union pstate_msr {
 #define PSTATE_DEF_CORE_FREQ_BASE	25
 
 /* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
-#define  SERIAL_VID_DECODE_MICROVOLTS	5000
-#define  SERIAL_VID_BASE_MICROVOLTS	245000L
+#define  SERIAL_VID_3_DECODE_MICROVOLTS	5000
+#define  SERIAL_VID_3_BASE_MICROVOLTS	245000L
 
 #define MSR_CPPC_CAPABILITY_1				0xc00102b0
 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF		24
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index 3a2157bea1..b7d954d982 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -154,8 +154,8 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
 		/* Voltage off for VID codes 0xF8 to 0xFF */
 		voltage_in_uvolts = 0;
 	} else {
-		voltage_in_uvolts =
-			SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
+		voltage_in_uvolts = SERIAL_VID_2_MAX_MICROVOLTS -
+					(SERIAL_VID_2_DECODE_MICROVOLTS * core_vid);
 	}
 
 	/* Power in mW */
diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h
index 83f5f0596f..2f0237204e 100644
--- a/src/soc/amd/picasso/include/soc/msr.h
+++ b/src/soc/amd/picasso/include/soc/msr.h
@@ -27,7 +27,7 @@ union pstate_msr {
 #define PSTATE_DEF_CORE_FREQ_BASE	25
 
 /* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */
-#define  SERIAL_VID_DECODE_MICROVOLTS	6250
-#define  SERIAL_VID_MAX_MICROVOLTS	1550000L
+#define  SERIAL_VID_2_DECODE_MICROVOLTS	6250
+#define  SERIAL_VID_2_MAX_MICROVOLTS	1550000L
 
 #endif /* AMD_PICASSO_MSR_H */