diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-06-01 23:22:11 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-07 00:30:13 +0000 |
| commit | 0b07e36a1fb7e48dc31aa6b630e3f7069a23e259 (patch) | |
| tree | 20d7754b4d2f44ef0a5bfa2d8185ff07db0a7f9d /src/soc/amd | |
| parent | f6421311c96fd3ffef0e9b4791c9c25a2f03d055 (diff) | |
soc/amd/stoneyridge/acpi: rename sb_fch.asl to mmio.asl
This file only contain the ACPI code describing the MMIO devices in the
FCH, so rename it to mmio.asl. This also brings the Stoneyridge ACPI
code a bit more in line with the ACPI code of the other SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iccef1fc5230e3e104d8dea586a9cbaf894471c12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75597
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/mmio.asl (renamed from src/soc/amd/stoneyridge/acpi/sb_fch.asl) | 0 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/soc.asl | 4 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/mmio.asl index ef2b4eab62..ef2b4eab62 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/mmio.asl diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl index 47d5992272..6e67f5a3fa 100644 --- a/src/soc/amd/stoneyridge/acpi/soc.asl +++ b/src/soc/amd/stoneyridge/acpi/soc.asl @@ -15,8 +15,8 @@ Scope(PCI0) { /* Describe PCI INT[A-H] for the Southbridge */ #include "pci_int.asl" -/* Describe the devices in the Southbridge */ -#include "sb_fch.asl" +/* Describe the MMIO devices in the FCH */ +#include "mmio.asl" /* Add GPIO library */ #include <soc/amd/common/acpi/gpio_bank_lib.asl> |