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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-05-31 20:26:16 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-06-11 07:11:43 +0000 |
| commit | dea42e011a126c4fdc9ab62f6d6c449df4740f82 (patch) | |
| tree | 97896aa5869a5447ecca0310af09d0e122729bfd /src/soc/amd/stoneyridge | |
| parent | a96be277e1062796be7109a08a9ab9cdb6bf5d28 (diff) | |
cpu/x86/lapic: Replace LOCAL_APIC_ADDR references
Note that there are assumptions about LAPIC MMIO location
in both AMD and Intel sources in coreboot proper.
Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index a2e719b978..d80aeb2a09 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -340,7 +340,7 @@ void amd_initcpuio(void) /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */ base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE; - limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP; + limit = (ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8) | MMIO_NP; pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit); pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base); |