From dea42e011a126c4fdc9ab62f6d6c449df4740f82 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 31 May 2021 20:26:16 +0300 Subject: cpu/x86/lapic: Replace LOCAL_APIC_ADDR references MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Note that there are assumptions about LAPIC MMIO location in both AMD and Intel sources in coreboot proper. Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194 Reviewed-by: Felix Held Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/northbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/amd/stoneyridge') diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index a2e719b978..d80aeb2a09 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -340,7 +340,7 @@ void amd_initcpuio(void) /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */ base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE; - limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP; + limit = (ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8) | MMIO_NP; pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit); pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base); -- cgit v1.2.3